APEX 20K Devices

31 Pages·2005·0.79 MB·English

APEX 20K Devices
•TheAPEX device familyrangesfrom30,000 to over1.5 milliongates(113,000 to over2.5 millionsystemgates) andshipson 0.22-µm, 0.18-µm, and0.15-µm
and0.15-µmprocesses.
•Introducedin 1999, theAPEX device familyextendedAltera's leadershipin embeddedPLD architecturesto newlevelsofefficiencyandperformance.
performance.
•APEX devicesare uniquelysuitedfor system-on-a-programmable-chip(SOPC) solutions, allowingdesignersto integratea systemefficientlyanduse itin a
anduse itin a broadrangeofapplications.
•Altera's APEX 20KC devicescombinea 0.15-µm, all-layer-copperinterconnectwithstate-of-the-art featuresfoundin APEX 20KE devices.
•MultiCore™architecturecombineslogicandmemoryfor high-densitySOPC solutions.
•Hardcopy solution
All-Layer Copper Interconnect Technology
APEX 20KC devices are the first FPGA family to feature all-layer copper interconnect
technology. All-layer copper interconnect technology uses copper for all metal layers,
optimizing the performance-critical high-speed interconnects typically found in metal
layers 1 through 5. Semiconductor devices that use copper for the top two metal layers
typically get no significant performance benefits because the top two layers are used for
power planes and do not affect the device performance
Architektura
Mega labs:
LE jednotky z FLEX 6000
Plus ESB
■Designed for low-power operation
– 1.8-V and 2.5-V supply voltage
– MultiVoltTM I/O interface support to interface with 1.8-V, 2.5-V,3.3-V, and 5.0-V
ESB offering programmable power-saving mode
■ Flexible clock management circuitry with up to four phase-locked
loops (PLLs)
– Built-in low-skew clock tree
– Up to eight global clock signals
– ClockLock® feature reducing clock delay and skew
– ClockBoost® feature providing clock multiplication and division
– ClockShiftTM programmable clock phase and delay shifting
■ Powerful I/O features
PCI Local Bus Specification,
– Bidirectional I/O performance (tCO + tSU) up to 250 MHz
– LVDS performance up to 840 Mbits per channel
– Direct connection from I/O pins to local interconnect providing
fast tCO and tSU times for complex logic
– MultiVolt I/O interface support to interface with 1.8-V, 2.5-V,
3.3-V, and 5.0-V devices (see Table 3)
– Programmable clamp to VCCIO
– Individual tri-state output enable control for each pin
– Programmable output slew-rate control to reduce switching
noise
– Support for advanced I/O standards, including low-voltage
differential signaling (LVDS), LVPECL, PCI-X, AGP, CTT, stubseries
terminated logic (SSTL-3 and SSTL-2), Gunning
transceiver logic plus (GTL+), and high-speed terminated logic
(HSTL Class I)
– Pull-up on I/O pins before and during configuration
■ Advanced interconnect structure
– Four-level hierarchical FastTrack® Interconnect structure
providing fast, predictable interconnect delays
– Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
– Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
– Interleaved local interconnect allows one LE to drive 29 other
LEs through the fast local interconnect
■ Advanced packaging options
– Available in a variety of packages with 144 to 1,020 pins
– FineLine BGA® packages maximize board space efficiency
■ Advanced software support
– Software design support and automatic place-and-route
provided by the Altera® Quartus® II development system for
Windows-based PCs, Sun SPARCstations, and HP 9000
Series 700/800 workstations
– Altera MegaCore® functions and Altera Megafunction Partners
Program (AMPPSM) megafunctions
– NativeLinkTM integration with popular synthesis, simulation,
and timing analysis tools
– Quartus II SignalTap® embedded logic analyzer simplifies
in-system design evaluation by giving access to internal nodes
during device operation
– Supports popular revision-control software packages including
PVCS, Revision Control System (RCS), and Source Code Control
System (SCCS )

ESB
• Embedded System Block Capability
• The ESB is the heart of the MultiCore architecture. Each ESB contains 2,048 programmable bits
that can be configured as product-term logic, LUT-based logic or three types of memory: dual-port
RAM, read-only memory (ROM), or content-addressable memory (CAM).
• Embedded Product-Term Logic
• Configuring the ESB for product-term logic provides a powerful level of integration that is unique
to APEX devices. Product-term logic has historically been superior for control logic functions such
as address decoding and state machines. The integrated product-term approach enables APEX
devices to achieve maximum efficiency and performance for these functions. Each APEX ESB
can be configured with up to 16 macrocells, similar to a streamlined subset of the MAX 7000 LAB.
Each ESB can contain up to 32 product terms, XOR logic, 16 D-flipflops, and parallel expanders.
• Embedded Dual-Port RAM
• The APEX ESB supports the wide range of RAM widths and depths required in a system-level
design and can be configured as 128 x 16, 256 x 8, 512 x 4, 1,024 x 2, or 2,048 x 1. ESBs can be
easily cascaded together to form wider and deeper memories. Like the EAB of FLEX 10KE
devices, the APEX ESB supports dual-port RAM with independent read/write ports, synchronous
or asynchronous access, and 161 MHz first-in first-out (FIFO) buffer performance. APEX 20KE
and APEX 20KC devices both support dual-port RAM. Table 1 shows how this system-level
memory integration efficiently supports the various RAM requirements of a system-level design,
such as cache RAM, dual-port FIFO buffers, or ROM.
• Content Addressable Memory
• CAM is a memory technology that accelerates search applications and
is widely used in high-speed communication applications. Unlike RAM,
which receives an address as input and outputs data, CAM takes a
data input and outputs the address. Each APEX ESB can be configured
as a 32-word by 32-bit CAM, and multiple ESBs can be cascaded to
support larger CAM blocks. APEX CAM, which can be configured in
APEX 20KE and APEX 20KC devices, is faster than traditional discrete
CAM because integrating the CAM into the PLD eliminates off- and on-
chip delays. For more information, see the APEX CAM page.