Analog Layout Generation for Performance and Manufacturability

185 Pages·1999·7.863 MB·English

by  Koen Lampaert, Georges Gielen, Willy Sansen (auth.)

ANALOG LAYOUT GENERATION FOR PERFORMANCE
AND MANUFACTURABILITY
THE KLUWERINTERNATIONAL SERIES
IN ENGINEERING AND COMPUTER SCIENCE
ANALOG CIRCUITS AND SIGNAL PROCESSING
Consulting Editor: Mohammed Ismail. Ohio State University
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ANALOG LAYOUT
GENERATION FOR
PERFORMANCE AND
MANUFACTURABILITY
by
Koen Lampaert
Katholieke Universiteit Leuven
Georges Gielen
Katholieke Universiteit Leuven
and
Willy Sansen
Katholieke Universiteit Leuven
SPRINGER SCIENCE+BUSINESS MEDIA, LLC
A C.I.P. Catalogue record for this book is available from the Library of Congress.
ISBN 978-1-4419-5083-3 ISBN 978-1-4757-4501-6 (eBook)
DOI 10.1007/978-1-4757-4501-6
Printed on acid-free paper
AII Rights Reserved
© 1999 Springer Science+Business Media New York
Originally published by Kluwer Academic Publishers, Boston in 1999
Softcover reprint ofthe hardcover Ist edition 1999
No part of the material protected by this copyright notice may be reproduced or
utilized in any form or by any means, electronic or mechanical,
including photocopying, recording Of by any information storage and
retrieval system, without written permission from the copyright owner.
Abstract
Analog integrated circuits are very important as interfaces between the digital parts of integrated
electronic systems and the outside word. A large portion of the effort involved in designing these
circuits is spent in the layout phase. Whereas the physical design of digital circuits is automated
to a large extent, the layout of analog circuits is still a manual, time-consuming and error-prone
task. This is mainly due to the continuous nature of analog signals, which causes analog circuit
performance to be very sensitive to layout parasitics. The parasitic elements associated with
interconnect wires cause loading and coupling effects that degrade the frequency behavior and
the noise performance of analog circuits. Device mismatch and thermal effects put a funda
mental limit on the achievable accuracy of circuits. For successful automation of analog layout,
advanced place and route tools that can handle these critical parasitics are required.
In the past, automatic analog layout tools tried to optimize the layout without quantifying the
performance degradation introduced by layout parasitics. Therefore, it was not guaranteed that
the resulting layout met the specifications and one or more layout iterations could be needed. In
this work, we propose a performance driven layout strategy to overcome this problem; In our
methodology, the layout tools are driven by performance constraints, such that the final layout,
with parasitic effects, still satisfies the specifications of the circuit. The performance degrada
tion associated with an intermediate layout solution is evaluated at runtime using predetermined
sensitivities. In contrast with other performance driven layout methodologies, our tools oper
ate directly on the performance constraints, without intermediate parasitic constraint generation
step. This approach makes a complete and sensible trade-off between the different layout alterna
tives possible at runtime and therefore eliminates the possible feedback route between constraint
derivation, placement and layout extraction.
Besides its influence on the performance, layout also has a profound impact on the yield
and testability of an analog circuit. In this work, we develop a new criterion to quantify the
detectability of a fault and combine this with a yield model to evaluate the testability of an in
tegrated circuit layout. We then integrate this technique with our performance driven routing
algorithm to produce layouts that have optimal manufacturability while still meeting their per
formance specifications.
Contents
Abstract v
1 Introduction 1
1.1 Mixed-signal Design Methodology . ......... 1
1.2 A Hierarchical Performance-Driven Design Strategy 3
1.3 Physical Design Tools for Mixed-signal IC's . 7
1.3.1 Circuit Level Layout Generation . . 7
1.3.2 System Level Layout Generation. . 7
1.3.3 Layout Extraction and Verification . 8
1.3.4 Scope Of This Work 9
1.4 Layout Styles ..... 9
1.4.1 Full-Custom .... 9
1.4.2 Semi-Custom .... 10
1.4.3 Scope Of This Work 11
1.5 Existing Tools for Analog Layout 11
1.5.1 The Analog Macro-Cell Layout Style 11
1.5.2 Implementations of the Macro-Cell Layout Style 13
1.5.3 Situation Of This Work. . . . . . . . 17
1.6 Overview of the Analog Layout Tool LAYLA 18
1.6.1 Circuit Analysis 19
1.6.2 Device Generation 19
1.6.3 Placement ..... 19
1.6.4 Routing ...... 19
1.7 Summary and Conclusions 20
2 Performance Driven Layout of Analog Integrated Circuits 21
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2 Problem Formulation ................... 21
2.3 Previous Work in Performance Driven Layout Generation . 25
2.3.1 Digital Performance Driven Layout Generation 25
2.3.2 Analog Performance Driven Layout Generation . 26
2.3.3 Discussion ............... 27
2.4 A Direct Performance Driven Layout Strategy . . . . . . 28
viii CONTENTS
2.4.1 Modeling Performance Degradation . . 29
2.4.2 Generation of Performance Sensitivities 29
2.4.3 Modeling of Layout Parasitics 32
2.5 Interconnect Parasitics ..... . 32
2.5.1 Interconnect Modeling .. 33
2.5.2 Equivalent Circuit Model . 33
2.5.3 Parasitic Extraction. 36
2.6 Device Parasitics .. . . 38
2.7 Mismatch ......... . 39
2.7.1 Mismatch Model .. 40
2.7.2 Layout Rules for Optimum Matching 41
2.8 Thermal Effects ............... . 43
2.8.1 Effect of Operating Temperature on Electrical Parameters 43
2.8.2 Thermal Analysis of Electronic Systems. 46
2.8.3 Discussion ........................ . 48
2.9 Substrate Coupling . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.9.1 Injection, Reception and Transmission of Substrate Current 48
2.9.2 Modeling of Substrate Coupling ........ . 49
2.9.3 Layout Measures to Reduce Substrate Coupling. 50
2.10 Summary and Conclusions ............... . 51
3 Module Generation 53
3.1 Introduction ......... . 53
3.2 Problem Formulation . . . . . 53
3.3 Module Generation Strategies 55
3.3.1 Fixed Library of Procedural Generators 55
3.3.2 Dynamic Merging .......... . 56
3.3.3 Simultaneous Placement and Module Optimization 56
3.3.4 Discussion . . . . . . . 57
3.4 Transistor Stacking Algorithms. 57
3.5 Procedural Module Generation 60
3.6 Technology Independence 60
3.7 Examples .......... . 61
3.7.1 MOS Transistor ... . 62
3.7.2 Cascode MOS Transistor Pair 68
3.8 Summary and Conclusions 68
4 Placement 71
4.1 Introduction 71
4.2 Problem Formulation . . . . . . 71
4.3 Overview of the Placement Tool 74
4.4 Previous Work in Placement Algorithms 75
4.4.1 Constructive Placement (CP) .. 76
CONTENTS ix
4.4.2 Force-Directed Placement (FDP) .... 76
4.4.3 Placement by Partitioning (PbP) 76
4.4.4 Quadratic Optimization (QO) . 76
4.4.5 Simulated Evolution (SE) ... 77
4.4.6 Simulated Annealing (SA) . . . 77
4.4.7 Discussion ............ . 78
4.5 Simulated Annealing for Analog Performance Driven Placement 80
4.5.1 Placement Representation .... . 80
4.5.2 Device Representation ............. . 83
4.5.3 Interconnect Area Estimation ........ . 85
4.6 Handling Analog Constraints in Simulated Annealing . . 87
4.7 Move Set ................. . 89
4.8 Cost Function . . . . . . . . . . . . . 94
4.9 Estimating Performance Degradation. . 95
4.9.1 Interconnect Parasitics .... . 96
4.9.2 Device Mismatch ....... . · . 100
4.9.3 Thermal Effects. . . . . . . . .. · .... 101
4.10 Dynamic Interconnect Area Estimation .. · .... 104
4.11 Annealing Schedule. . . . . . . . . . . . · .... 105
4.12 Experimental Results ...... . . .. 107
4.12.1 Comparator. · . 107
4.12.2 Opamp1 .. . · .... 111
4.12.3 Opamp2 .. . · .... 113
4.12.4 Opamp3. . . · . 115
4.13 Summary and Conclusions · 118
5 Routing 119
5.1 Introduction .. · 119
5.2 Problem Formulation . . . . . .. · . 119
5.3 Overview of the Routing Tool .. · 120
5.4 Classification of Routing Algorithms. · . 121
5.4.1 Routing Strategy · . 121
5.4.2 Routing Model ....... . · 122
5.4.3 Search Strategies . . . .. · . 123
5.5 Previous Work in Area Routing ... . · . 124
5.5.1 Maze Routing ........ . . ..... 124
5.5.2 Line-Search Routing . . ...... 125
5.5.3 Line-Expansion Routing .. . · 125
5.5.4 Discussion ......... . · . 126
5.6 A Grid-Less Maze Routing Algorithm · . 126
5.6.1 Routing Model ...... . · . 127
5.6.2 Source Region Expansion · 130
5.6.3 Path Expansion . . . . ... · . 131
x CONTENTS
5.7 Cost Function . . . . . . · 134
5.7.1 Actual Path Cost · 134
5.7.2 Predictor Term · 136
5.7.3 Symmetric Routing . · 136
5.7.4 Multi-Terminal Nets · 137
.......
5.8 Net Scheduling · 138
5.8.1 Pre-Routing Phase · 139
5.8.2 Performance Driven Routing Phase · 139
5.8.3 Manufacturability Phase · 140
5.9 Estimating Yield and Testability · 140
5.9.1 Yield Modeling . · 141
5.9.2 Testability. . · 145
5.10 Experimental Results · 147
5.10.1 Opampl .. · 147
5.10.2 Opamp2. . . · 150
5.10.3 CPUTimes . · 152
5.11 Summary and Conclusions · 152
6 Implementation 153
6.1 Introduction . · 153
6.2 Implementation . . . · 153
6.2.1 Source Code · 153
6.2.2 Interface to Electronic Design Frameworks · 154
6.3 Use ofLAYLA in an Industrial Environment. · 155
6.3.1 Link to Schematic Capture . . . . . . · 155
..........
6.3.2 Link to Simulation · 155
6.3.3 Back-Annotation of Layout Parasitics · 156
...............
6.4 Results ...... · 156
7 General Conclusions 159
Bibliography 163
List of Tables
4.1 Comparator: performance characteristics ........... . · 107
4.2 Comparator: offset voltage . . . . . . . . . . . . . . . . . . . . · 108
4.3 Opamp1: performance characteristics obtained after placement. · 112
4.4 Opamp2: performance characteristics. . . . . . . . . . . . . . . · 113
4.5 Performance characteristics of the class NB operational amplifier · 115
4.6 Opamp3: offset voltage. . . . . . . . . . . . . . . . . . . . . . . · 115
5.1 Opamp 1 : Performance and Test Error Rate. . . . . . . . . . . . . 148
5.2 Performance and Test Error Rate for Opamp2 after performance-driven routing
(Stage 1) and after yield and testability optimization (Stage 2). . . . . . . . . .. 150
5.3 Execution times for the different layout generation steps for test circuits OpampJ
and Opamp2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 152