Analog IC Reliability in Nanometer CMOS

207 Pages·2013·4.75 MB·English

by  Elie Maricau

Analog Circuits and Signal Processing
Series Editors
Mohammed Ismail, The Ohio State University
Mohamad Sawan, École Polytechnique de Montréal
For furthervolumes:
http://www.springer.com/series/7381
Elie Maricau Georges Gielen
•
Analog IC Reliability
in Nanometer CMOS
123
Elie Maricau Georges Gielen
ESAT-MICAS ESAT-MICAS
KULeuven KULeuven
Heverlee Heverlee
Belgium Belgium
ISBN 978-1-4614-6162-3 ISBN 978-1-4614-6163-0 (eBook)
DOI 10.1007/978-1-4614-6163-0
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(cid:2)SpringerScience+BusinessMediaNewYork2013
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Abstract
Today, micro-electronic circuits are undeniably and ubiquitously present in our
society. Transportation vehicles such as cars, trains, buses, and airplanes make
abundantuse ofelectroniccircuitstoreduce energyconsumptionandemissionof
greenhouse gases and to increase passenger safety and travel comfort. Other
products using electronic circuits are smartphones, tablet PCs, game consoles,
household appliances, satellites, base stations, servers, etc. Each of these appli-
cations is becoming increasingly more complex to build. At the same time, the
quality and reliability requirements for electronic circuits are more demanding
than ever.
To guarantee a high production yield and a sufficient circuit lifetime, possible
hazardsandfailureeffectshavetobeconsideredthroughouttheentiredesignflow.
Such a flow includes the initial concept, the design itself, the testing of the pro-
totype circuit, and finally the production process. The majority of integrated cir-
cuits manufactured today is processed in a complementary metal-oxide
semiconductor (CMOS) technology. To reduce cost and to increase performance,
the dimensions of all circuit components are shrinked with each new technology
node. Associated with this technology scaling are the atomistic size of modern
transistors,anincreaseofthegate-oxideelectricfield,andtheintroductionofnew
gate and channel materials. The combination of these elements results in an
emerging reliability problem for advanced nanometer CMOS technologies.
Transistorwearoutmanifestsitselfasagradualandtime-dependentshiftofcircuit
characteristicswhichcanresultincircuitfailure.Especiallyanalogcircuits,which
aretypicallyusedasaninterfacebetweentherealworldandadigitalbackend,can
be very sensitive to such small circuit parameter variations.
This work focuses on the simulation and analysis of analog circuit reliability.
The models and simulation techniques proposed in this dissertation are aimed to
serveasanaidforcircuitdesignerstobetterunderstandtheimpactofagingeffects
ontheircircuitsandtoenablethedevelopmentoffailure-resilientdesignsolutions.
In a first part of the work, an overview of all relevant nanometer CMOS
unreliabilityeffectsisgivenandtransistorcompactmodelsforthemostimportant
v
vi Abstract
aging effects are proposed. A distinction between spatial unreliability effects,
resulting from process variations, and temperoral unreliability effects, which are
time-dependent,canbemade.Thelattercanagainbedividedintotransienteffects
such as noise and electromagnetic interference, and aging effects such as break-
down, bias temperature instability, and hot carrier injection. This work primarily
concentrates on the aging effects. To enable efficient and accurate circuit lifetime
simulations, transistor compact models for each aging effect are proposed. These
models include the most important circuit-related stress parameters such as volt-
ages, transistor dimensions, and temperature. Important effects such as partial
recovery of the transistor damage when the stress voltage is reduced, are also
supported. Each model is validated with measurements. Also, models for sto-
chastic aging effects in sub-45 nm CMOS, which result in time-dependent tran-
sistor mismatch, are discussed.
A second part of the book focuses on the development of efficient simulation
methods to analyze the impact of transistor aging on an entire circuit. Existing
reliability simulators, published in the literature or commercially available, still
suffer from a lot of deficiencies. Often, these tools do not supportall unreliability
effectsandespeciallytheimpactofprocessvariationsandstochasticagingeffects
is in most cases not included. The tool set presented in this work aims to solve
these problems, while still limiting the computational effort. The proposed simu-
lator includes support for all important deterministic and stochastic aging effects.
Further, the interaction between process variations and aging effects can be ana-
lyzed and visualized. In addition to a visualization of the time-dependent perfor-
mance shift of the circuit under test, reliability weak spots can be detected. This
enablesadesignertosearchfordedicatedsolutionsincaseofareliabilityproblem.
To limit the simulation time, the simulator uses a response surface method which
models the time-dependent circuit performance based on only a limited set of
SPICE-based reliability simulations. Finally, a hierarchical simulation framework
based on an adaptive sample selection algorithm and a nonlinear symbolic
regression algorithm enables the reliability simulation of large analog circuits
within a reasonable time frame. Each part of the simulation framework is dem-
onstrated on an example circuit.
The last part of this work applies the proposed reliability compact models and
simulation methods to a set of commonly used analog circuits. Factors that
determinethecircuitlifetimeareexploredandillustratedwithexamples.Further,a
designforreliabilityflowisdemonstratedonanexampleIDACcircuitresultingin
the design of a reliable circuit with minimum guardbanding. Finally, the lifetime
of small- to medium-sized digital circuits is investigated. Although, the methods
proposed in this work are primarily intended for analog circuits, they are also
applicabletosmall-andmedium-sizeddigitalcircuitswhenthesearedefinedasa
SPICE netlist.
Themodelsandsimulationtechniquesdevelopedinthisworkareintendedasa
firststeptowardsunderstandingtheimpactoftransistoragingonanalogintegrated
circuits.Eventually,thisunderstandingcanhelpdesignersindesigningguaranteed
reliable and robust circuits in future CMOS process nodes.
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Reliability Engineering: A Brief History . . . . . . . . . . . . . . . . . 1
1.3 Reliability of Electronic Systems. . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Reliability in Nanometer CMOS . . . . . . . . . . . . . . . . . . . . . . . 5
1.4.1 Reduction of the Effective Oxide Thickness. . . . . . . . . . 5
1.4.2 Introduction of New Materials and Devices . . . . . . . . . . 7
1.4.3 Atomic-Scale Dimensions . . . . . . . . . . . . . . . . . . . . . . 8
1.4.4 Mission Profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4.5 Time and Money Constraints . . . . . . . . . . . . . . . . . . . . 9
1.5 Design for Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.5.1 Define. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5.2 Identify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.5.3 Analyze and Assess. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.5.4 Quantify, Improve and Validate . . . . . . . . . . . . . . . . . . 13
1.5.5 Monitor and Control . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2 CMOS Reliability Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 The Origin of CMOS Unreliability . . . . . . . . . . . . . . . . . . . . . 15
2.3 Spatial Unreliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.1 Systematic Effects. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.2 Random Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4 Temporal Unreliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.4.1 Aging Effects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.4.2 Transient Effects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
vii
viii Contents
3 Transistor Aging Compact Modeling . . . . . . . . . . . . . . . . . . . . . . 37
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.2 Hot Carrier Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2.2 A HCI Compact Model for Circuit Simulation. . . . . . . . 40
3.2.3 HCI in Sub-45 nm CMOS . . . . . . . . . . . . . . . . . . . . . . 46
3.3 Bias Temperature Instability. . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.3.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.3.2 A BTI Compact Model for Circuit Simulation . . . . . . . . 55
3.3.3 Model Calibration and Validation. . . . . . . . . . . . . . . . . 61
3.3.4 BTI in Sub-45 nm CMOS . . . . . . . . . . . . . . . . . . . . . . 68
3.4 Time-Dependent Dielectric Breakdown . . . . . . . . . . . . . . . . . . 69
3.4.1 Hard Breakdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.4.2 Soft Breakdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.5 Aging-Equivalent Transistor Model. . . . . . . . . . . . . . . . . . . . . 73
3.5.1 Threshold Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.5.2 Carrier Mobility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.5.3 Oxide Breakdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.6 Aging Model for Hand Calculations . . . . . . . . . . . . . . . . . . . . 75
3.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4 Background on IC Reliability Simulation . . . . . . . . . . . . . . . . . . . 79
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.2 Literature Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.2.1 Berkeley Reliability Tools (BERT). . . . . . . . . . . . . . . . 80
4.2.2 Other Reliability Simulators. . . . . . . . . . . . . . . . . . . . . 83
4.3 Commercial Reliability Simulators . . . . . . . . . . . . . . . . . . . . . 84
4.3.1 The Mentor Graphics Reliability Simulator . . . . . . . . . . 84
4.3.2 The Cadence Reliability Simulator (BERT/RelXpert) . . . 86
4.3.3 The Synopsys Reliability Simulator (MOSRA). . . . . . . . 87
4.4 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5 Analog IC Reliability Simulation . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.2 Deterministic Reliability Simulation . . . . . . . . . . . . . . . . . . . . 94
5.2.1 Problem Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.2.2 Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.2.3 Circuit Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.3 Stochastic Reliability Simulation. . . . . . . . . . . . . . . . . . . . . . . 109
5.3.1 Problem Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.3.2 Implementation 1: Monte-Carlo Simulation . . . . . . . . . . 112
5.3.3 Implementation 2: A Response Surface Methodology . . . 115
Contents ix
5.3.4 Circuit Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.4 Hierarchical Reliability Simulation . . . . . . . . . . . . . . . . . . . . . 136
5.4.1 Problem Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
5.4.2 Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.4.3 Circuit Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
5.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
6 Integrated Circuit Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
6.2 Assessment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
6.2.1 Observed Performance Parameter . . . . . . . . . . . . . . . . . 153
6.2.2 Process Capability Index . . . . . . . . . . . . . . . . . . . . . . . 155
6.2.3 Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
6.2.4 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
6.2.5 Stress Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
6.3 Failure-Resilient Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
6.3.1 Intrinsically Robust Circuits. . . . . . . . . . . . . . . . . . . . . 161
6.3.2 Self-healing Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 163
6.4 Case Study 1: IDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
6.4.1 Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
6.4.2 Conventional Design. . . . . . . . . . . . . . . . . . . . . . . . . . 167
6.4.3 Reliability-Aware Design: Fixed Topology. . . . . . . . . . . 168
6.4.4 Reliability-Aware Design: Digitally-Assisted Analog. . . . 170
6.5 Case Study 2: Digital Circuits. . . . . . . . . . . . . . . . . . . . . . . . . 171
6.5.1 Digital Circuit Lifetime. . . . . . . . . . . . . . . . . . . . . . . . 172
6.5.2 Minimum Circuit Lifetime. . . . . . . . . . . . . . . . . . . . . . 173
6.5.3 Example Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
6.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
7 Conclusions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
7.1 General Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Bibliography. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Abbreviations
AC Alternating Current
ADC Analog-to-Digital Converter
AEC Automotive Electronics Council
ALT Accelerated Life Test
AMS Analog and Mixed Signal
BERT Berkeley Reliability Tools
BSIM Berkeley Short-channel IGFET Model
BTI Bias Temperature Instability
CDF Cumulative Density Function
CMOS Complementary Metal-Oxide-Semiconductor
CHE Channel Hot Electron
CP Charge Pumping
DAC Digital-to-Analog Converter
DAHC Drain Avalange Hot Carrier
DC Direct Current
DFR Design For Reliability
DPT Design Patterning Technology
DUT Device Under Test
eMSM extended Measurement Stress Measurement
EM ElectroMigration
EMI ElectroMagnetic Interference
ENOB Effective Number Of Bits
EOT Effective Oxide Thickness
EUVL Extreme Ultraviolet Lithography
ESD ElectroStatic Discharge
FET Field Effect Transistor
FF Fractional Factorial
FFX Fast Function eXtraction
FMEA Failure Mode Effect Analysis
FTC Fast Transient Charging
GBW Gain-BandWidth
xi