Analog IC Design An Intuitive Approach (Chapters 1-8)

203 Pages·2016·11.3 MB·English

by  Gabriel Alfonso Rincón-Mora

Analog IC Design
Analog IC Design
– An Intuitive Approach –
Gabriel Alfonso Rincón-Mora
Georgia Institute of Technology
Rincon-Mora.gatech.edu
Chapters
T
X
TE 1. Microelectronic Systems
N
O
C
2. Microelectronic Devices
N
O 3. Single-Transistor Primitives
TI
A
D
UN 4. Analog Building Blocks
FO U❉ N H
5. Negative Feedback
6. Operational Amplifiers
N
O
TI
A7. Comparators
C
LI
P
P
A8. Reference Circuits
Final Notes on Analog IC Design
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Analog IC Design
1.1. Emerging Applications
Applications: Bio-monitors, micro-sensors, pacemakers, cochlear processors,
10–200 µW
defibrillators, hearing aids, reconnaissance, micro-robots, remote meters,
Peak to 5–10 W 02–2 mW 1–10 mW Micro-sensor
neural recorders/stimulators, retinal implants, and others.
1–100 mW 40–250 mW
Requirements: Useful, unobtrusive, and economical.
Smart (e.g., low-power sensor, processor, transmitter, etc.)
Portable (i.e., small and compact) ot
b
o
Lightweight o-r
cr
Mi
Self-powered (with onboard power source)
Self-sustained (with ambient energy) or
nit
Silicon microchip (i.e., on-chip, in-package, mo
o-
Bi
and on-package integration)
1.2. Technological Constraints
Portable and Unobtrusive àSmall Footprint: 1 Microchip
Low Breakdown Voltages à Low Supply Voltages: 1–1.8 V
High Integration à Diverse Power Levels: nW's to W's
à Diverse Supply Voltages: 0.5–2 V
Low Filter Density à Low C /µm2 ≤ 15 fF/µm2
MAX
E.g.: 1 nF requires 260 × 260 µm2
à L ≤ 40–100 nH
MAX
Noise-Sensitive (analog) Blocks à Accurate and Fast Supplies:
Δv ≤ 10–100 mV
SUPPLY(DC–RIPPLE–DUMPS)
High Silicon (wafer) Density à Digital VLSI (CMOS) and
Mixed-Signal (BiCMOS) Microchips
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Analog IC Design
Parameter Specifications Simulated Perf. Meas. Perf. Un
Min. Typ. Max. Min. Typ. Max. Mean Sigma
1.3. System VLio♥ueta (ro Rveer❣aulll ❛a(cid:0)cocruracy) 2.85 3 3.15 2.87 3.1 3.05 0.1 V
Line Regulation 10 3 7 10 2 m
Requirements Load Regulation 50 42 45 5 m
Short Ckt. Current 0 250 225 30 m
✶✁
Refer ce
❡♥
Low breakdown voltage and low battery voltage à Low supply headroom (margin).

Long life, little board space, and no heat sinks à Low power consumption.
Accurate and high performance, but with low dynamic range (low signal/noise ratio).

On chip à High power-packing density, low exposure to high voltages, and
low interface power (i.e., less parasitic capacitance to charge and discharge).
Cross-coupled, substrate-injected, and electronic noise à Suppress noise.
Noisy supply à Reject supply noise à High power-supply rejection.
I.e.: Highly functional: complex, fast, accurate, low cost: CMOS and few components,
small: SoC/SiP/SoP, long life: low power, reliable: few transistors, etc.
1.4. Objectives
Present, discuss, and show how to understand, develop, and use
semiconductor devices to design analog integrated circuits (ICs).
Develop and illustrate how to model, analyze, and design analog ICs
using bipolar, CMOS, and biCMOS technologies.
Develop basic understanding and critical-thinking skills, in other words,
insight and intuition for how semiconductor devices work
individually and collectively in microelectronic circuits.
Furnish a physical and insightful view of solid-state circuits that
transcends rigorous mathematical and algebraic formulations
to empower the engineer with the tools necessary
to design practical, high-performance, and innovative ICs.
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Analog IC Design
Chapter 2. Microelectronic Devices
Outline
2.1. Resistors
2.2. Capacitors
2.3. PN-Junction Diodes
2.4. Bipolar-Junction Transistors
2.5. Metal–Oxide–Semiconductor Field-Effect Transistors
2.6. Junction Field-Effect Transistors
2.7. Practical Considerations
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Analog IC Design
2.1. Resistors: A. Theory of Operation
Materials (diffusion, poly-silicon, etc.) offer resistance to charge carriers.
Resistance rises with length L and falls with cross-sectional area A (i.e., W T ).
X X X X
Sheet Resistance
RX=ρAXLXX =TρXXWLXX RS=ρTXX RX=R❙!"#WLXX$%&=R❙NX
(of one square)
ρX ≡ Resistivity WX and LX are design variables. NX ≡ Number of Squares
Parasitics
v =i R P =i v
R R X R R R
A dielectric isolates resistors from substrate à Parasitic C in all R's.
PAR
B. Physical Layout:
i. Unmatched
R ≈ 7R
X S
Dog-Bone Structure

For high resistances,
use narrow
serpentine resistors à
Approximation:
10 corners can be
roughly equivalent
to 5 squares.
Usually, R is 20–500 Ω/Square and tolerance is ±20%.
S
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Analog IC Design
ii. Matched
Eliminate
corner No Corners
mismatch.
Reduce
gradient Close Array
effects. (square)
Reduce
Wide Strips
edge
mismatch. Dummy Strips RA = 2RB
Common Centroid
Average and match effects
of two-dimensional gradients. Interdigitated Strips and Statistical Spread
This way, resistors can match within 0.5% to 1%.
Cross-coupling components into a modular/square array
reduces maximum distance d and related nonlinear spread effects.
MAX
No corners
Close Array
Wide Strips
Dummy Strips
Common Centroid
R ≡ R + R + R + R = R + R + R + R ≡ R
A A1 A2 A3 A4 B1 B2 B3 B4 B
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Analog IC Design
2.2. Capacitors: A. Theory of Operation
An electric field ξ induces charge flow (i.e., current i )
FLD C
and disconnected parallel plates accumulate charge q ,
C
so the field (i.e., voltage v ) across the plates rises.
C
Capacitance C is how much charge q the device holds
P C
(i.e., permits) with a voltage v .
C
q dq " %
C☎=vCC ∴ qC=C☎vC and iC≡ ❞✂C =CP#$❞❞✄✂C&'
I.e.: An electric field ξ across parallel plates
FLD
holds (i.e., stores) charge (i.e., energy).
Larger surface areas A = W L collect more charge and
P P P
less separation d intensifies the field and attracts more charge,
P
∴ C rises with higher W and L and lower d .
P P P P
"A % !WL $ ε ≡ Permitivity
CP=#$dPP&'εP="# dPP P&$kPε0=WPLPCε" W and L are design variables.
P P
dv dt 1
ΔiC causes ΔvC ∴ Capacitors offer impedance: ❩C≡ diC =C →sC
C P P
Parasitics
Plates offer resistance à Parasitic R in all C's.
P
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Analog IC Design
B. Physical Layout: Matched
Top View
C = C
A B
Overlap bottom plate to reduce edge variation to that of one plate à Top place sets C.
Improve Matching Performance:
Large Area and Dummy Strips (shown) Common Centroid (not shown)
Statistical Spread (not shown) Cross-Coupled Devices (not shown)
Typical tolerance is ±20% and matching can be within 0.5% to 1%.
Thin oxide (TOX) separates top–bottom capacitor plates.
Capacitor sits on thick field oxide (FOX).
The same layers of dissimilar structures do not always align.
Capacitor

Matching Top Plate

Misaligned

To minimize mismatches from dissimilar peripheries
like "etching effects", ensure peripheries match and align.
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Analog IC Design
2.3. PN-Junction Diodes: (3)
A. Theory of Operation
(1)
(2)
(4) i = –i ∴ i = 0.
DIFF DRIFT D
Energy-Band
Diagram
Conduction Energy E : Electrons e– above E are loosely bound ∴ Available.
C C
Valence Energy E : e– below E are tightly bound ∴ Only holes h+ are available.
V V
No charge carriers across the "band-gap" energy E .
BG
Fermi Energy E : Highest probability of finding a charge carrier at 50%.
F
Probability of finding a charge carrier falls exponentially away from E .
F
Lightly doped regions are easier to deplete à Depletion width ∝ 1/N .
DOPANTS
Forward-biasing junction with v > 0 reduces barrier ∴ i ∝ exp(v ).
D D D
Raising v pushes holes toward depletion region ∴ d shortens.
P DEP
i –v Curve
D D
⎡ ⎛v ⎞ ⎤
✐D=■✆⎣⎢exp⎝⎜VDt⎠⎟−1⎦⎥∝AJ
Reverse-biasing with v < 0 raises barrier ∴ i ≈ I ∝ Junction Area A à Near 0.
D D S J
Lowering v pulls holes away from depletion region ∴ d lengthens.
P DEP
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