Analog circuit design : fractional-N synthesizers, design for robustness, line and bus drivers

395 Pages·2003·29.4 MB·English

by  Workshop of Advances in Analogue Circuit Design (12th : 2003 : Graz, Austria)

ANALOG CIRCUIT DESIGN
Analog Circuit Design
Fractional-N Synthesizers,
Design for Robustness, Line and Bus Drivers
Edited by
Arthur van Roermund
Eindhoven University ofTechnology, The Netherlands
Michiel Steyaert
KU Leuven, Belgium
and
Johan H. Huijsing
Delft University ofTechnology, The Netherlands
KLUWER ACADEMIC PUBLISHERS
NEW YORK,BOSTON, DORDRECHT, LONDON, MOSCOW
eBookISBN: 0-306-48707-1
Print ISBN: 1-4020-7559-6
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Table of Contents
Preface vii
Part I: Fractional-N Synthesis
A. van Roermund 1
Practical Design Aspects in Franctional-N Frequency Synthesis
W. Rhee 3
Design and Simulation of Franctional-N Frequency
Synthesizers
M. Perrott 27
Monolithic CMOS Fractional-N Frequency Synthesizer Design for
High Spectral Purity
B. De Muer, M. Steyaert 51
A 19mW 2.2GHz Fully Integrated CMOS Sigma Delta Fractional
Synthesiser with 35Hz Frequency Step and Quantization Noise
Compensation
I. Bietti, G. Albasini, E. Temporiti, R. Castello 77
Implementation Aspects of Fractional-N Techniques in
Cellular Handsets
Y. Le Guillou, D. Brunel 97
Fractional-N Phase Locked Loops and it’s Application in the GSM
System
G. Märzinger, B. Neurauter 111
Part II: Design for Robustness
M. Steyaert 129
ESD for Analogue Circuit Design
D. Clarke, A. Righter 131
ESD in Smart Power Processes
G. Croce, A. Andreini, L. Cerati, G. Meneghesso, L. Sponton 169
vi
RF-ESD Co-Design for High Performance CMOSLNAs
P. Leroux, M. Steyaert 207
Improvement of System Robustness through EMC
Optimazation
B. Deutschmann 227
Robustness in Analog Design
M. De Mey 243
Minimizing Undesired Coupling and Interaction in Mixed Signal ICs
T.J. Schmerbeck 255
Part III: Line and Bus Drivers
J. Huijsing 273
Looking to/for Low Power ADSL Drivers in the DSLAM
E. Moons 275
Class-AB Low-Distortion Drivers for ADSL
T. Ferianz 291
Class D Self-Oscillating Line Drivers
T. Piessens, M. Steyaert 309
Class G/H Line Drivers for xDSL
J. Pierdomenico 333
The USB 2.0 Physical Layer: Standard and Implementation
G. den Besten 359
Backplane Transceivers
K. Tam, W. Ellersick, R. Soenneker 379
PREFACE
This book contains the revised and extended tutorials that 18 experts have
presented at the workshop on Advances in Analog Circuit Design
(AACD) held at 15-17 April 2003, in Graz, Austria. The book comprises
three parts, one per topic, each with 6 tutorial contributions. The three
topics are:
Fractional-N Synthesis;
Design for Robustness;
Line and Bus Drivers.
Each topic is introduced with a foreword by the chairman of the day,
respectivelyArthur van Roermund, Michiel Steyaert, and Han Huijsing.
Together, they form the permanent program committee of AACD. The
local organising committee of the workshop was formed this year by
Herbert Grünbacher(workshop chairman) from Carinthia Tech Institute,
Villach, Austria; Wolfgang Pribyl from Austriamicrosystems; and Franz
Dielacher from Infineon Technologies.
This book is number 12 in the series called Analog Circuit Design. The
topics discussed in previous issues are:
AACD 2002 Spa (Belgium)
Structured Mixed-Mode Design
Multi-Bit Sigma-Delta Converters
Short-Range RF Circuits
AACD 2001 Noordwijk (The Netherlands)
Scalable Analog Circuits
High-Speed D/A Converters
RF Power Amplifiers
AACD 2000 Munich (Germany)
High-Speed A/D Converters
Mixed-Signal Design
PLLs and Synthesizers
AACD 1999 Nice (France)
XDSL and Other Communication Systems
RF-MOST Models and Behavioural Modelling
Integrated Filters and Oscillators
viii
AACD 1998 Copenhagen (Denmark)
1-Volt Electronics
Mixed-Mode Systems
LNAs and RF Power Amps for Telecom
AACD 1997 Como (Italy)
RF A/D Converters
Sensor and Actuator Interfaces
Low-Noise Oscillators, PLLs and Synthesizers
AACD 1996 Lausanne (Swiss)
RF CMOS Circuit Design
Bandpass SD and Other Converters
Translinear Circuits
AACD 1995 Villach (Austria)
Low Noise/Power/Voltage
Mixed-Mode with CAD Tools
Voltage, Current and Time References
AACD 1994 Eindhoven (The Netherlands)
Low Power, Low Voltage
Integrated Filters
Smart Power
AACD 1993 Leuven (Belgium)
Mixed-Mode A/D Design
Sensor Interfaces
Communication Circuits
AACD 1992 Scheveningen (The Netherlands)
Opamps
ADC
Analog CAD
We hope that also the current book in this series will provide a valuable
contribution to our Analog Circuit Design community.
Arthur van Roermund
PART I: FRACTIONAL-N SYNTHESIZERS
Fractional-N synthesis refers to the synthesis of a reference frequency that is
related with a fractional ratio to another reference frequency. This is
especially important in RF communication electronics, where oscillator
frequencies have to be tuned to specific RF frequencies, while coupled to a
highly accurate reference frequency, most commonly with a phase-locked
loop (PLL). If an integer divider is used in the feedback loop, the reference
frequency has to be kept very low to obtain enough frequency resolution,
which has drawbacks like strong noise gain and, because of stability reasons,
low-bandwidth loops, and thus slow lock-in behaviour. Fractional-N dividers
provide a solution here, but if simply done by changing temporarily between
two integer values, this results in strong phase perturbations, and therefore in
strong undesired phase noise and frequency spurs in the output spectrum. A
solution is found in sigma-delta modulation, which can shape the errors in
the frequency domain. An optimal trade-off can thus be made between
resolution, spectral purity, switching speed, and power dissipation. However,
the combination of PLL design, sigma-delta design, and RF circuit design
aspects makes this a complex job. Moreover, secondary effects, like noise
modulation by non-linear parasitic non-linearities, appear to be significant
for high performance integrated RF circuits.
The tutorials that follow all comprise some overview of theory and
application of fractional-N synthesis and show experimental verification of
it, but from different angles and with different focus. The first paper of Rhee
is a general introductory paper including practical design considerations, and
a treatment of noise coupling, non-linear effects and out-of-band noise
problems. The second paper, of Perrott, focuses on design and simulation
techniques and tools, at transfer-function level and detailed behavioural
level. The third paper, of De Muer, specifically addresses a fast non-linear
analysis method, and shows that due to non-linear effects a single-loop
architecture yet has preference over a MASH architecture, and that for high-
resolution applications the limitations of fractional-N sigma-delta become
apparent. The last three papers are more application oriented. The paper of
Bietti focuses on specific designs, down to transistor level, for wireless 3G
terminals. The paper of Guillou specifically shows the application in receiver
I/Q mixers, UMTS local oscillators, and variable IF in transmitters. The last
paper, of Märzinger, addresses the use of fractional-N sigma-delta loops for
highly integrated modulators: the fractional-N control input is heredriven by
the signal that is to be modulated.
Arthur van Roermund
PRACTICAL DESIGN ASPECTS IN
FRACTIONAL-N FREQUENCY SYNTHESIS
Woogeun Rhee
IBM Thomas J. Watson Research Center
Yorktown Heights, NY, USA
Abstract
The objective of this work is to present practical design consideration
of fractional-N frequency synthesis focusing on different aspects
from integer-N frequency synthesizer design. In this work, a frac-
tional-Nfrequency synthesis technique for high spectral purity is pri-
marily considered. The fractional-N synthesizer offers several
advantages over integer-N synthesizers and conventional fractional-
N synthesizers. However, superior performance of the fractional-
N synthesizer can be possibly limited by noise coupling, nonlinearity,
and out-of-band phase noise performance. Design efforts and system
perspectives both for the modulator and the PLL are needed to
overcome those issues. System and circuit design aspects in frac-
tional-N synthesizer design have been addressed followed by exper-
imental hardware results.
1. Introduction
The demand for low-cost high-performance frequency synthesizers is growing as
wireless systems are diversified. High data-rate systems such as general packet
radio service (GPRS) need agile frequency switching and require lower in-band
phase noise to maintain the same integrated phase error with wider loop
bandwidth. Standard frequency synthesizers based on a PLL have difficulties in
meeting various specifications due to the fundamental trade-off between loop
bandwidth and channel spacing. The circuit noise floor of the synthesizer and
spurious tones can be suppressed by narrowing the PLL bandwidth, but the
narrowband PLL suffers from long settling time. The narrow loop bandwidth also
3
A. van Roermund et al. (eds.), Analog Circuit Design, 3-26.
© 2003 Kluwer Academic Publishers. Printed in the Netherlands.