An Injectable 64 nW ECG Mixed-Signal SoC in 65 nm for Arrhythmia Monitoring

16 Pages·2014·4.64 MB·English

IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.50,NO.1,JANUARY2015 375
An Injectable 64 nW ECG Mixed-Signal SoC in
65 nm for Arrhythmia Monitoring
Yen-Po Chen,StudentMember,IEEE, Dongsuk Jeon,StudentMember,IEEE, Yoonmyung Lee,Member,IEEE,
Yejoong Kim,StudentMember,IEEE, Zhiyoong Foo, InheeLee,StudentMember,IEEE, NicholasB. Langhals,
Grant Kruger, Hakan Oral, Omer Berenfeld, ZhengyaZhang,Member,IEEE, David Blaauw,Fellow,IEEE,and
DennisSylvester, Fellow, IEEE
Abstract—A syringe-implantable electrocardiography (ECG)
monitoringsystemisproposed.Thenoiseoptimizationandcircuit
techniques in the analog front-end (AFE) enable 31 nA current
consumption while a minimum energy computation approach in
thedigitalback-endreducesdigitalenergyconsumptionby40%.
TheproposedSoCisfabricatedin65nmCMOSandconsumes64
nWwhilesuccessfullydetectingatrialfibrillationarrhythmiaand
storing the irregular waveform in memory in experiments using
anECGsimulator,alivesheep,andanisolatedsheepheart.
Index Terms—Analog front-end (AFE), asynchronous logic,
capacitive feedback chopper stabilized instrumental amplifier
(CCIA), electrocardiography (ECG), fast Fourier transform
(FFT), implantable system, kickback noise, minimum energy
point(MEP),mm .
I. INTRODUCTION
E LECTROCARDIOGRAPHY(ECG)istherecordofelec-
trical activity in the heart and serves as a critical source
of information for the diagnosis and study of many heart dis- Fig.1. (a)ECGwaveformshowing 60Hzinterferingnoise asrecorded by
proposedsystem.(b)SheepECGwaveformsuffersfromlow-frequencydrift
orders.Arrhythmiaisoneofthemostprevalentheartdiseases.
(measuredbyproposedsystem).Notethatthegainisreducedby inthis
Inparticular,accordingtoa2010NationalInstitutesofHealth measurement.
report[1],2.7millionpeoplesufferfromatrialfibrillation(AF),
whichisthemostcommontypeofarrhythmia,andthenumber
a handfulof seconds. Consequently,in arrhythmia studiesand
ofpeopleimpactedcontinuestoincreaseovertime[1].
treatment, long-term but fast observation is essential to assess
In ECG waveform with AF, normal-shaped peaks (dubbed
theabnormalityanditsseverity[2].
QRS complexes) corresponding to the ventricles are seen, but
To enable ECG monitoring, body-wearable systems are a
with an irregular rhythm, but the peaks corresponding to the
widelyusedsolutionforlongtermobservation.Twoormoreof
atrial activity (dubbed P waves) are either abnormal in shape
patchesareattachedtotheskinandconnectedtoabody-wear-
and/or size, appear at fast irregular rates and/or non-discrete.
able device for continuously monitoring the ECG and storing
Therefore,bymonitoringtherateandshapeirregularitiesonthe
thewaveformondemand.However,therearesomechallenges
ECG,AFcanbedetected.However,arrhythmiacanoccurvery
in arrhythmia monitoring when using such an approach. First,
rarely(e.g.,onlyafewtimesaday)witheacheventlastingonly
even small body-wearable systems severely impact a patient’s
everyday life. Second, physical contact between patches and
ManuscriptreceivedApril29,2014;revisedJuly20,2014,andSeptember
theskincansufferfromimpedancechangesduetobodymove-
28,2014;acceptedOctober14,2014.DateofpublicationNovember14,2014;
dateofcurrentversionDecember24,2014.ThispaperwasapprovedbyGuest ment, which results in low frequency baseline wander of the
EditorDavidStoppa.ThisworkwassupportedinpartbytheNationalHeart, output voltage, degrading signal quality and even saturating
Lung,andBloodInstituteunderGrantR01-HL118304,theLeducqFoundation,
the amplifier [3]–[5]. Third, the signals captured using such
theCoulterandMTRACprogramsfromtheUniversityofMichigan,andthe
NationalScienceFoundation,DARPA/StartNetTerraswarmResearchCenter. systems are prone to coupled noise from outside sources such
Y.-P.Chen,D.Jeon,Y.Kim,Z.Foo,I.Lee,G.Kruger,Z.Zhang,D.Blaauw, as 60 Hz noise from power lines. Example ECG waveforms
andD.SylvesterarewiththeUniversityofMichigan,AnnArbor,MI48105
showinginterferencefrom60Hznoiseandexhibitinglow-fre-
USA.
Y.LeewaswiththeUniversityofMichigan,AnnArbor,MI48105USA.He quencywanderingareshowninFig.1.
isnowwithSungkyunkwanUniversity,Suwon110-745,Korea. Incontrast,implantedsystemscanbeanattractivealternate
N.B.Langhals,H.Oral,andO.BerenfeldarewiththeUniversityofMichigan
solution; modern devices have a form factor roughly compa-
HealthSystem,AnnArbor,MI48105USA.
DigitalObjectIdentifier10.1109/JSSC.2014.2364036 rabletoaUSBflashdrive[6].Sincethesedevicesareinserted
0018-9200©2014IEEE.Personaluseispermitted,butrepublication/redistributionrequiresIEEEpermission.
Seehttp://www.ieee.org/publications_standards/publications/rights/index.htmlformoreinformation.
376 IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.50,NO.1,JANUARY2015
undertheskin,theimpactonpatientdailylifeisdramaticallyre-
ducedonceinstalled.Thisapproachalsooffersstablephysical
contact between electrodes and the tissue. The signal strength
andqualitydegradationduetothesmallerelectrodespacingrel-
ativetoasurfacepatch-basedrecordingapproachesiscompen-
sated by subcutaneous embedding and proximity to the heart,
yielding similar signal quality to wearable devices as will be
shownlater.Moreover,thesubcutaneousdeviceislesssuscep-
tible to noise sources outside the body. However, the major
drawback of implanted systems is the need for expensive and
risky surgery. Device lifetime is also critical and is often re-
quired to be several years; as a result, a large battery and low
power system are needed. To extend lifetime for both body
wearableandimplantablesystems,therehasbeenasignificant
focusonlow-powerECGsystems,forexample,in[7]–[15].
Toaddressthissetofchallenges,thispaperproposesasmall
form-factorsyringe-injectableECGrecordingandanalysisde-
vice targeted primarily at atrial fibrillation arrhythmia moni-
toring.Thedevicecanbeinjectedundertheskinneartheheart
usingasyringeneedletoavoidsurgerywhileretainingtheben-
efitsofanimplantablesystem.
The paper is organized as follows. Section II provides an
Fig.2. (a)MeasuredQRSpeakamplitudeversuselectrode(useneedlesasthe
overview of the system. Section III describes the analog front electrodesdirectly)separationundertheskininasheepexperiment.Notethat
end while Section IV discusses the digital back end of the with cmseparation,theamplitudeislargerthanthetraditionalapproach
withtwopatchesattachedtoneckandwrist.(b)Dimensionsoftheproposed
system. Section V presents the result of several experiments
system.
using the proposed system. Section VI then concludes the
paper.
The ability of the system is focus on low power consumption
II. OVERVIEWOFTHESYSTEM and arrhythmia monitoring depends in part on efficient algo-
rithms. The system consists of analog signal acquisition and
A. DimensionoftheSystem digital back end blocks. The signal from electrodes is filtered,
amplified, and converted to the digital domain by an analog
System size is determined as follows: to achieve a syringe-
frontend(AFE).Adigitalsignalprocessing(DSP)moduleana-
implantable design, the entire system must pass through the
lyzesthewaveformwithina10-ssearchwindowanddetectsab-
14-gaugesyringeneedleduringtheimplantation.Hence,thede-
normalcardiacevents.Wheneveranabnormaleventisdetected,
vice width is limited to 1.5 mm. In contrast, the length is less
the device stores the current search window waveform (
constrainedandthetwoelectrodesattachedtoeithersideofthe
down sampled) into local memory; it can then be transferred
device require 2 cm separation [Fig. 2(a)] in order to provide
to an external device through means such as a wireless trans-
sufficientseparationtoyieldanacceptablylargepotentialdiffer-
ceiver for further analysis by clinicians. It is also compatible
ence.Thetargetdimensionsoftheproposedsystemareshown
withotherultralow-powersensornodeperipheralsasshownin
in Fig. 2(b).
Fig. 3(b) [16].
Furthermore, the size constraint also severely limits battery
sizeandhenceitscapacity.Therefore,incontrasttosurgically
implanteddevicessuchaspacemakerswithlargebatteries,the
proposed device is designed for daily wireless recharging, en- III. IMPLEMENTATIONOFTHEAFE
ablingamuchsmallerbattery.Whilethepatientsleeps,ahost
Fig. 4 shows the AFE top level block diagram. The AFE
station [depicted in Fig. 3(a)] near the bed could recharge and
consistsofthreeblocks:alow-noiseinstrumentationamplifier
retrieve the stored data through a wireless channel. The life-
(LNA), a variable-gain amplifier (VGA), and a successive ap-
time between recharging is set to be five days to provide a
proximation register analog-to-digital converter (SAR ADC).
safety margin. Matching battery size to device size allows for
To reduce power consumption, the AFE supply voltage is 0.6
a5 Ahr,3.7mm Libattery,whichconstrainssystempower
VandallbuildingblocksexcepttheADCsclockedcomparator
consumption to be less than 167 nW. This represents a chal-
are biased in the subthreshold regime for low power and high
lengingpowerconstraintgiventhatcomparablesystemsinthe
currentefficiency.Notethat thelowsupplyvoltagemay incur
literaturetypicallyconsume1–30 W[7]–[14].
non-linearityinthefinaloutputsignal,especiallyintheampli-
fierstage.However,basedonsimulationresultsfinalarrhythmia
B. SystemOverview
detectionisunaffectedwith %(THD)nonlinearity.There-
TheproposedECGmonitoringSoCis1.4mmwideandcon- fore,thenonlinearitydesigntargetissetto3%fortheAFEto
sumes 64 nW while continuously monitoring for arrhythmia. bestbalancesystemperformanceandpowerconsumption.
CHENetal.:INJECTABLE64NWECGMIXED-SIGNALSOCIN65NMFORARRHYTHMIAMONITORING 377
St.Paul,MN,USA)].Fig.5(a)showsthatwitharelaxednoise
constraint, AFE power consumption reduces significantly, but
thereceiveroperatingcharacteristics(ROC)curvesinFig.5(b)
demonstrate that the detection accuracy drops as well. Never-
theless, the proposed system and detection algorithm suffers
no performancedegradation(100% sensitivityandspecificity)
with up to 15 V input-referred noise. As a result, the design
is targeted to 15 V input-referred noise to minimize power
consumptionwhilemaintaininghighatrialfibrillationdetection
accuracy. In the final design, the amplifier specification is
tightenedto10 Vinput-referrednoiseacrossprocesscorners
to allow for a 10 V ADC noise budget. This optimization
reduces AFE power by from 132 to 17 nW and system
power by from 177 to 72 nW, compared with typical
ECG signal acquisition designs that require noise levels of
3 V. Due to the resulting high-performance variability
and the possibility of the environmental and process changes,
the amplifier gain, bandwidth, and input-referred noise can be
adjusted by the digital blocks to maximize the useful signal
range.
B. AmplifierImplementation
As shown in the AFE top-level diagram, two amplifiers are
used in series to provide low noise and high gain. The first
amplifier focuses on low noise while the second amplifier en-
ablestunablegain.Duetothelargetissue-electrodeimpedance
(measuredtovaryfrom1to5M acrossdifferentinstancesof
thesamemodelofelectrodes,with 4 average)theinput
amplifier requires very high input impedance. In addition, the
signal is located in the flicker noise bandwidth and requires
Fig.3. (a)Proposednightlyreadoutandrechargeofthesystem.(b)Otherre-
chopper stabilization [21]. Therefore, a capacitive feedback
quiredperipheral.
chopper-stabilized instrumental amplifier (CCIA) topology
is employed for the first-stage amplifier to ensure high input
impedance and low noise. The design targets of the CMRR
A. NoiseSpecification
and PSRR are set to be higher than 80 dB as the standard
Similar to other noise-limited amplifier designs [17], the requirement of the ECG amplifier [18], [19]. The target input
total power consumption of the analog front end is dominated impedance is set to be larger than 10 M to have sufficient
by the first stage of the LNA. Typical ECG designs usually signal amplitude similar to [22]. The target gain is set to be
target extremely low input referred noise level [around 3 V 72 dB and design to be tunable to provide sufficient gain to
[18], [19]; see the red dashed line in Fig. 5(a)] for best signal amplifythe1mVpeaktopeaksignaltorail-to-railoutputand
quality.However,duetothedirectrelationshipbetweencurrent tunabledynamicrange.Theamplifieralsotargetathandlingthe
consumption and input referred noise,this leads to currentsof dc offset up of the electrodes to 300 mV as required standard
larger than 100 nA assuming a noise efficiency factor (NEF) [19]bycapacitiveinput.Fig.6providesadiagramoftheCCIA.
of 3 and 500 Hz bandwidth. In order to reduce total power, Thecapacitivefeedbackprovidesfixed40dBgain,andparallel
weoptimizeamplifierperformancebyobservingitsimpacton resistive feedback generates the high-pass corner to filter out
thefinalproposedarrhythmiadetectionaccuracy.Theeffectof dc offset and low-frequency drift of the signals. To generate a
noise levels on the accuracy of binary classification between Hzultralowhigh-passcornerwithreasonablechiparea,
atrial fibrillation and normal sinus rhythm was assessed by apseudo-resistorisemployed.
applying our atrial fibrillation detection algorithms [20] (see To further boost input impedance, a positive feedback
Fig. 14 and Section IV-B below) on the collected ECG wave- impedanceboostingloop(IBL)similarto[22]isimplemented.
forms with artificial additive white Gaussian noise (AWGN) The IBL generates a current similar to the input current to the
at various levels (from 0 to 40 V). The collected ECG coreamplifierandfeedsitbacktotheinputtocompensatethe
waveforms were collected from 40 un-discriminated patients input current and increase the input impedance. The amplifier
that were referred to the University of Michigan hospital for shown in the figure in the impedance boosting loop serves is
diagnosisandtreatmentofatrialfibrillationandthenoiselevels design to avoid unwanted signalfeeding through the feedback
added was designed to surpass the typical ECG noise level path.SincetheinputoftheamplifierintheIBLisanamplified
[ECGswererecordedduringanEPprocedureundersupineand signal,thisamplifierisnotnoiselimited.Therefore,500pAis
sedation condition by an EP-Med System (St. Jude Medical, allocatedwithlittleimpactontheoverallpowerbudget.
378 IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.50,NO.1,JANUARY2015
Fig.4. Top-leveldiagramoftheanalogfrontend.
Fig.5. (a)Tradeoffbetweenamplifiercurrentconsumptionandinputreferrednoiseassumedconstant(NEF).(b)Theerrorrateacrossdifferentnoiselevelswith
sweepingthreshold.Inthisplot,theX-axisistruenegativerateandtheY-axisistruepositiverate.Thelinepassthrough showninthe15 V
caseimplythatthereisathresholdexistedwithoutanyerrorindetection.Otherlinewithoutpassing implythereisatleastonefalsealarmwhen
allthea-fibarrhythmiaisdetectedforanypossiblethreshold.
To remove harmonics from the chopper, a Gm-C filter is thefeedbacknetwork.Therefore,asecondamplifierstageisre-
implemented in the next stage with 250 Hz bandwidth. Note quiredwithinthecoreamplifier.Sincethesubsequentamplifier
that the chopper is inserted in front of to reduce the receivesanamplifiedsignal,thenoiseconstraintissignificantly
mismatch of and improve the CMRR of the amplifier, relaxed;thisstageconsumesonly500pAandallowstheCCIA
as in [23]. to achieve 61 dB gain overall. Simulation results of the CCIA
Fig.7showsthecoreamplifieroftheCCIA.Thefirststage overallgainareshowninFig.8.
amplifieruses20nAcurrenttomeetthenoiserequirementdis- Acommonissuewithinverter-basedamplifierdesignisvul-
cussedinSectionIII-A.Thiscurrentcanbetunedbya4-bitbi- nerability of the bias point to PVT variations. Therefore, a dc
narycodefromthedigitalbackendtomatchthedesirednoise servoloop(DSL),similarto[22],isadoptedtostabilizethedif-
level(rangingfrom3to12 V).Toefficientlyusethecurrent, ferentialoutputandreduceoffsetbyfixingthedcoutputtohalf
an inverter-based amplifier topology, similar to [24], [25], is .Fromsimulationresults,theDSLreducesdcoffsetfrom
adopted to achievelow NEF.Common mode feedback ispro- 1.52 to 0.071 mV.
videdbyboththebottomNMOSandthepseudoresistors(used TableIsummarizestheperformanceofthesimulatedCCIA.
toimplementa 0.1Hzfilter),guaranteeingtheoutputcommon Themidbandgainis39dBwith250Hzbandwidth(limitedby
modestaysathalf . theGm-Cfilterforthechoppers).Throughtheuseofchopping,
Fromsimulation,thefirststageamplifiergainis32dB,which the impedance boosting loop, and the DSL, all ECG amplifier
isnotsufficienttoprovidetheoverall40dBgaintargetthrough requirementsaremet.
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Fig.8. SimulatedCCIAgainversusfrequency(withoutGm-Cfilter).
TABLEI
SIMULATEDSPECIFICATIONSOFTHECCIATOGETHERWITHGM-CFILTER
Fig. 6. First stage of the low-noiseamplifier, including allbuilding blocks:
chopper,dcservoloop,andimpedanceboostingloop.
Fig.9. (a)SARADCpowerbreakdownwithADClogicimplementedusing
HVTstandardcells.NotethatSARlogicconsumes92%oftotalpowerwhenop-
eratingat500Hz.(b)SARADCpowerbreakdownwithcustomasynchronous
logic.
Fig.7. CoreamplifierinsidetheCCIA.
anti-aliasingGm-Cfilterisbuiltwitha500pAamplifierinfront
of the ADC.
C. ECGSARADCOverview
AlthoughSARADCconsumeslesspowercomparedtoam-
Thesystem’sanalogtodigitalconversionisperformedbyan plifierintheECGsystem,thelongtermgoalofthemm system
8bitsingle-endedasynchronousSARADCwith500Hzsam- [16] is to build aplatform for all theavailable sensors. There-
plingrate.Toavoidaliasfromotherfrequencyband,a250Hz fore,theminimizationsofthepowerconsumptionareconducted
380 IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.50,NO.1,JANUARY2015
Fig.10. DetailedsignalflowdiagramoftheasynchronouscontrollerinsidetheSARADC.
Fig.11. DetaileddiagramofasynchronuslogicintheSARADC.Notethatsomeoftheresetpathandthedoublestackedtransistors(toreduceleakage)arenot
shown.
ateachbuildingpartseparatelyincludingtheADC.Powercon- 50%oftotalenergyconsumptioncomesfromdigitallogicdue
sumption of the SAR ADCs are well studied in recent years. toleakageandlongcycletimes.ThisisincontrasttomostSAR
However,mostpriorworkfocusesonhighsamplingratesthat ADCswhichoperateatmuchhighersamplerateandhencehave
farexceedtherequirementsofthisECGsystem.Amongthose powerdominatedbyDACswitching.Theimportanceofdigital
SAR ADCs that operate in the kHz range and offer nW-level logicinthisapplicationwillbeheightenedduetothesub-kHz
power consumption [26]–[28], it is found that approximately samplingrates;simulatedpowerconsumptionofastandard8b
CHENetal.:INJECTABLE64NWECGMIXED-SIGNALSOCIN65NMFORARRHYTHMIAMONITORING 381
Fig.12. (a)Traditionalcomparatorandsourceofkickbacknoise.(b)Proposedcomparatorwithsuppressedkickbacknoisesources.
500 S/s SAR ADC is shown in Fig. 9(a). Here, standard cells implementedwithadelaylinesettobelongerthantheexpected
areusedforthedigitallogicandleakageisthemainsourceof DAC settling time across all corners. Since a long delay line
powerconsumptioninthedigitalblock. canalsoconsumehighpower,I/OHVTdevicesareusedtore-
ducethenumberofstagesandsavepower.OncetheDAChas
D. ImplementationofSARControlLogic settled, the “Comp” signal goes high and sends a comparator
Toreducedigitalpowerconsumption,anovelasynchronous clocksignaltotriggerthecomparison.Afterthecomparisonre-
logic is proposed to reduce transistor count and hence the sultisgenerated,“comp_result”and“comp_done”aresentby
leakagepowerofSARlogic.Conventionalasynchronouslogic thecomparator.ThecontrollersavestheresultintotheDACand
is typically implemented with dynamic logic to achieve peak raisesthe“bit_set”signalforthenextstage.
energy efficiency [29]. However, dynamic logic is not well Thetransistorscountoftheproposeddesignis34compared
suitedtolow-frequencyapplicationsduetoleakage.Therefore, withthe48transistorsofthetraditional2DFFdesign,and29%
in this work, all dynamic nodes are implemented with latches of reduction is achieved. To further reduce power, all leakage
clockedbyinternalsignalsanddelaylines. paths are double stacked, reducing subthreshold leakage by
Fig.10showsthedetailedsignalflowofaone-bitcontroller from163to85pW.AsshowninFig.9(b),theproposed
asanexample.Therearefourinternalsignals:1)the“bit_set” asynchronous logic reduces simulated power consumption to
signal implies the operation of the previous bit is done; 2) the 85 pW, marking a (from 918 to 85 pW) improvement
“DAC” signal is connected to the DAC and toggles the DAC comparedwithSARlogicusingsynthesizedstandardcells.
directly; 3) the “DAC_rdy” signal is triggered after the DAC
E. ImplementationofDACandComparator
is settled and ready for comparison; and 4) the “comp” signal
requestsacompareeventinthecomparator. Considering theimpact of mismatch [30] and thermalnoise
Oncetheresultofthelastbitcomparisonisdone,the“bit_set” onADCaccuracy,a10fFDACunitcapacitorandtypicalsplit
signalispulledupbythepreviousstage.Thecircuittopullup capacitorarraytopologyarechosen.Further,thecomparatoris
the“bit_set”signalisshownatthebottomleftofFig.11.The a clocked one-stage design that is chosen for its low dynamic
“DAC”signalisthensetto1bythecircuitshowninthebottom power consumption. However, the combination of first stage
rightofFig.11(notethattheDACissetto0initiallyandfloating clocked comparator and small capacitor array make the com-
nodesarecompletelyavoidedthroughtheuseoflatches).Once paratorinputvulnerabletokickbacknoise.Theproposeddesign
the DAC is settled, “DAC_rdy” goes high. Since direct detec- usesasplitfootercomparator[31]combinedwithcross-coupled
tionoftheDACsettlingto8bitaccuracywouldconsumesig- compensationtoaddressthisissue.Fig.12showstheschematic
nificant energy, the circuit triggering the “DAC_rdy” signal is oftheproposedcomparator.Notethatthekickbacknoisemainly
382 IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.50,NO.1,JANUARY2015
interval. The variance of peak-to-peak intervals is then cal-
culated. As the peaks are generated more irregularly during
arrhythmia, we apply a simple thresholding technique to the
varianceto detect an abnormal activity.Asa second approach
we perform arrhythmia detection in the frequency domain.
Undernormalconditions,peaksaregeneratedatapproximately
constant intervals, which translate to a clear dominant fre-
quencyandharmonicsinthefrequencyspectrum.However,as
showninFig.14(b),underabnormalrhythm,asingledominant
frequencyislessprominentandthefrequencyspectrumshows
moredispersion.Therefore,underarrhythmiasuchasatrialfib-
rillation,peakshavevaryingintervalsinthefrequencydomain,
and the arrhythmia can be detected by inspecting the variance
of intervals. The stored 50 Hz sampled waveform is sufficient
for detection of fast rhythms such as atrial fibrillation in the
frequency domain, where cardiac activation rate is always
25 Hz, but it is not suitable for time domain analysis where
precision of 40 ms is required, such as in sequential QRS
intervalsdetections.Thus,thestored50Hzsampledwaveforms
maynotbesuitableforsomeclinicalinterpretations.
Fig. 15(a) shows an overview of the digital back-end based
on the two detection algorithms described earlier. First, input
samples taken from the ADC output pass through the moving
averagefilter (MAF) of600mstoremoveslowbaselinewan-
deringbysubtractingtheoutputofMAFfromtheoriginalinput
toobtainfilteredresult.Atthesametime,thecircuitsensethe
inputcodesfromtheADCandtunesthegainsuchthattheswing
iswithin75%to90%oftheADCoutputrange.Therearetwo
separate processing paths for the frequency- and time-domain
algorithms.Inthetime-domainR-Ralgorithm,thefeatureisthe
Fig.13. Simulatedwaveformsofkickbacknoiseintheproposedandtradi- distancebetweenadjacentQRSpeaks,anditusesthevariance
tionalcomparators.Kickbacknoiseinthetraditionalamplifieris19.8mVand of these intervals to detect irregular peaks. The frequency-do-
isreducedto0.2mVintheproposeddesign.
mainFDMalgorithm[20]directlylooksatthefrequencyspec-
trumandchecksifthereexistsclearpeakswhichrepresentcon-
stantintervals.FurtherdetailsaregivenbelowinSectionIV-C.
stemsfromtherapidlychangedrainandsourcevoltagesofthe
inputtransistor.Intheproposeddesign,thesechangesarelim-
B. ImplementationofR-RDetection
itedto 100mVandtheresidualkickbacknoiseisreducedby
The proposed design can also perform standard QRS-peak
thecompensationtransistors.InthesimulationresultsofFig.13,
detection[32](R-Rblock),whichusespeak-to-peakdistances
thekickbacknoiseisreducedby (from19.8to0.2mV)
to determine ECG signal regularity. The input signal goes
intheproposedcomparatordesign.
through the bandpass filter based on an 80-tap FIR filter. The
TableIIshowsthepowerbreakdownofthecompleteanalog
signal is then differentiated to obtain the slope. If the signal
block.NotethatADCpowerisdominatedbytheanti-aliasing
slope exceeds a threshold a QRS peak is declared. The vari-
filterduetotheuseoflow-powerasynchronouslogic.
ance of R-to-R intervals is directly used as a decision value
IV. IMPLEMENTATIONOFDIGITALBACKEND in arrhythmia detection. The bus interface can program the
algorithms and retrieve the stored data when an arrhythmia is
A. OverviewoftheDigitalAlgorithm detected. This data is passed to peripherals on the other chips
The back-end digital block first detects the incoming signal through the data bus. The implemented design allows for one
amplitudeandtunesAFEgainaccordinglytosetthewaveform of the two different algorithms to be run, allowing for power
to full range. Arrhythmia detection is performed in a moving savingsbypowergatingtheunselectedprocessingpath.
10swindow,asshowninFig.14(a).Sincetheirregularsession
C. ImplementationoftheFrequencyDispersionMetric(FDM)
lastsseveralseconds,thereisnooverlappingbetweenthewin-
dows.Ifanarrhythmiaisdetectedinawindow,the down- The proposed FDM detects an arrhythmia in the frequency
sampled10swaveformistemporarilystoredinthememoryand domain.Theinputisfirstdown-sampledby ,andstoredin
aninterruptsignalissentoutforfurtherprocessing. one of two 0.6 kB ping-pong buffers. A 512-point real-valued
The first implemented detection algorithm is conventional FFTacceleratorisimplementedwitharadix-4256-pointcom-
time-domain detection [32]. This approach first detects the plex-valuedFFTshowninFig.16.First,theBlackman–Harris
largest QRS peaks and then calculates the peak-to-peak time windowobservingthe3–15Hzfrequencyrangeisappliedtothe
CHENetal.:INJECTABLE64NWECGMIXED-SIGNALSOCIN65NMFORARRHYTHMIAMONITORING 383
Fig.14. (a)Searchwindowsoftheproposedalgorithm.(b)ExamplewaveformofnormalECGwaveformandthearrhythmiaECGwaveform.(c)Corresponding
powerspectrumoftheECGwaveformsshownin(b).Notedthattheblockfloatingpointschemeisimplementedandthey-axisisshowingrelativenumberswithout
unit.
TABLEII tochanginglevelsofactivity,sincetheirregularpeaksfromar-
SIMULATEDPOWERBREAKDOWNOFAFE rhythmiausuallygeneratefasterandabruptchangescompared
with normal changes from changing levels of activity. The al-
gorithmscandistinguishitbychoosingrightdecisionvaluesin
thethresholdstage.
D. OptimizationforMinimumEnergyComputation
To further reduce energy consumption of the FDM block a
technique called minimum energy computation [33], [34] is
applied. As the supply voltage is lowered both leakage and
dynamic power reduce. However, the system clock is slowed,
and the leakage energy per cycle increases. Eventually, the
leakageenergyincreaseovercomesthedynamicenergysavings
andtotalenergystartstoincrease.Therefore,ithasbeenshown
signal, then the FFT block will calculates the frequency spec- that an optimal point exists, i.e., the minimum point of the
trum,andtheARMCortex-M0 coreperformstheactualdetec- plot in Fig. 15(b). In simulation, and are 300 and
tionalgorithmtoobservetheexistenceofthedominantpeaksin 250 mV, whereas we could achieve the same performance as
aspecificfrequencyrange,whichrepresentsastableheartbeat. in simulation at 400 mVinmeasurementduetodiscrep-
Once an arrhythmia is detected, the ping-pong buffer storing ancybetweensimulationandmeasurement.Andtheenergyper
thelastsearchwindownolongeracceptsnewsamplesuntilthe operation is 797 pJ/op at . Arrhythmia detection is done
waveformisfullyreadoutthroughadatabus.Duringthistime, onlyonceina10swindow,andeachdetectiontakesapproxi-
theother buffer actsasthe primary input datachannel.There- mately500cycles.Hence,500Hzinputsamplingfrequencyis
fore, the ping-pong buffers, along with the local buffer of the sufficienttomeetperformanceconstraintsandischosenforthe
FFT,makecontinuousarrhythmiadetectionpossiblewhiletem- proposed system. However, the minimum supply voltage that
porarily storing any previous abnormal activity. Note that the matchesthisfrequencyconstraintliesbelowtheenergyoptimal
ARMcoreinstructionmemorycanbeuser-programmedtopro- pointandthereforeconsumessubstantialleakageenergydueto
videaddedflexibilitysuchaschangestothepeakdetectional- the corresponding long cycle time. Therefore, we use a faster
gorithminthefrequencyspectrumorthefrequencymonitoring (10 kHz) clock and operate the detection in burst-mode (
window.Todealwithfalsealarmofchangesintheheartratedue faster than required). After the detection event completes the
384 IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.50,NO.1,JANUARY2015
Fig.15. (a)Topleveloftheproposeddigitalbackend.(b)Energy/operationversusvoltageshowstheminimumenergypointoftheFDMblock.
Fig.16. BlockdiagramofFFT,peripheralbuffers,andcontroller.
entireblock,includingtheFFTandM0 core,ispowergated achieves 2.64 NEF with 31 nA current consumption and 6.52
withanNMOSheaderusingaboostedenablesignal.Although V input-referred rms noise. The measured amplifier gain
a higher operating voltage is needed for this faster clock ranges from 51 to 96 dB with 250 Hz bandwidth. The fre-
frequency, the leakage energy per computation is greatly re- quency response of the amplifier is shown in Fig. 18. The
ducedandminimumpossibleenergyconsumptionisachieved. amplifier CMRR and PSRR are measured to be 55 and 67
Compared to the supply voltage corresponding to just-in-time dB, respectively. The measured SNR and THD with 0.5 mV
computation,thistechniqueincreasessupplyvoltageby50mV peak-to-peak input sine wave with rail-to-rail output are 48.6
whilereducingenergyby40%. dB and 2.87% ( 30.8 dB).
ThemeasuredmaximumDNLandINLoftheSARADCare
V. MEASUREMENTRESULTS and respectively.Notethatthenonlinearityresulted
fromtheDNLandINLarestilllessthantheamplifiernonlin-
A. ProposedAFEMeasuredResults
earity as shown in the SNDR. The SNDR and the ENOB are
Fig.17(a)isthechipmicrophotographoftheproposedSoC, 44.8 dB and 7.14 bits respectively. The FOM of the ADC is
and Fig. 17(b) shows the chip inside the syringe needle. It 25.5 fJ/conv-step. The SNDR of the entire AFE are 30.7 dB
is fabricated in 65 nm LP CMOS technology. The amplifier whichisdominatedbythenonlinearityoftheamplifier.