an improved method and apparatus for automated design and verificaton of integrated circuits

108 Pages·2017·2.1 MB·English

by  Dragomir M. Nikolic

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2005
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Dragomir M. Nikolic
University of Kentucky, [email protected]
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Nikolic, Dragomir M., "AN IMPROVED METHOD AND APPARATUS FOR AUTOMATED DESIGN AND
VERIFICATON OF INTEGRATED CIRCUITS" (2005). University of Kentucky Master's Theses. 268.
https://uknowledge.uky.edu/gradschool_theses/268
This Thesis is brought to you for free and open access by the Graduate School at UKnowledge. It has been
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For more information, please contact [email protected].
AN IMPROVED METHOD AND APPARATUS FOR AUTOMATED DESIGN AND
VERIFICATON OF INTEGRATED CIRCUITS

by

Dragomir M. Nikolic

This thesis is submitted to the faculty at the College of Engineering, University of
Kentucky in partial fulfillment of the requirements for the degree of

MASTER OF SCIENCE

in

Electrical Engineering

Director: Dr. J. Robert Heath, Associate Professor of Electrical and Computer
Engineering

Lexington, Kentucky
2005
Copyright © Dragomir Nikolic 2005
ABSTRACT OF THESIS

AN IMPROVED METHOD AND APPARATUS FOR AUTOMATED DESIGN AND
VERIFICATON OF INTEGRATED CIRCUITS

Electronic Design Automation (EDA) tools have always played an important role in Very
Large Scale Integrated (VLSI) Circuit development. Two major linked roles are to
reduce total design cycle time of Integrated Circuits (ICs) and increase profitability.
Profitability can significantly be increased through quicker development and shorter time
to market which in turn can be achieved through design automation. In addition to
design cycle time reduction, design automation provides consistency and repeatability,
which are critical for capturing and sharing of efficient design methods. Application
Specific Integrated Circuit (ASIC) development and verification is a very manual and
time consuming process. The objective of this research is to improve a design’s
parameters, such as silicon area, timing and power, while achieving design cycle time
reduction, through design and implementation of a new action and event-driven flow
automation tool. This novel approach to providing a quick and easy method for rapid
prototyping and automated verification without need for upgrading individual tools, can
lead to great design improvements with very limited upfront investment. The
automation tool is developed using a range of programming languages including SKILL
(a derivative of LISP), C/C++ and Tool Command Language (TCL). Design and
implementation, via use of the tool, are verified through hardening of a 32 bit, low power
processor core block while showing design cycle time speedup >7x and reduction in
total chip area by more than 20%. Supported and used software tools include: Cadence
Silicon Ensemble Place and Route, Signal Integrity, Physical Verification, Cross-Talk
Analysis and Abstract Generation; Synopsys Static Timing Analysis (STA); Mentor
Graphics Physical Verification, Parasitic Resistance and Capacitance (RC) Extraction.

__________________________

__________________________

Copyright © Dragomir Nikolic 2005
ACKNOWLEDGEMENTS

First of all, I want to thank my wife Heather and our three boys, Vladislav, James and
Gabriel for their support and patience during my graduate studies and this research.
Secondly, I would like to thank Cypress Semiconductor for the opportunity to participate
in the described cutting edge research and development, numerous reviews with
members of the design community as well as their provision of numerous computing
and software resources. Thirdly I would like to thank Ronald Kalim, my co-worker and
friend who participated on this project and helped develop code implementation for my
software design. I would also like to thank my advisor Dr. J. Robert Heath for his input,
guidance and support during this project. Finally, I would like to thank members of my
committee Dr. Henry Dietz and Dr. Joseph Elias for their time, feedback and guidance.

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TABLE OF CONTENTS

ACKNOWLEDGEMENTS ..............................................................................................III
TABLE OF CONTENTS.................................................................................................IV
TABLE OF FIGURES....................................................................................................VII
CHAPTER 1. INTRODUCTION....................................................................................1
1.1 Background.......................................................................................................1
1.2 Problem Statement...........................................................................................2
1.3 Additional ASIC Flow Background....................................................................4
1.3.1 Past ASIC Design Cycle............................................................................4
1.3.2 Present ASIC Design Cycle.......................................................................5
1.3.3 Future ASIC Design Cycle.........................................................................7
1.4 Definition of Terms............................................................................................7
CHAPTER 2. REQUIREMENTS................................................................................11
2.1 Scope..............................................................................................................11
2.2 Customers.......................................................................................................11
2.3 User Requirements.........................................................................................11
2.3.1 Functional Requirements.........................................................................11
2.3.2 Environment and Hardware.....................................................................16
2.3.3 Performance and Capacity......................................................................17
CHAPTER 3. ARCHITECTURE.................................................................................18
3.1 Knowledge Bases...........................................................................................19
3.1.1 Vendor Tool Knowledge Base .................................................................19
3.1.2 Design Knowledge Base..........................................................................19
3.1.3 Technology Knowledge Base ..................................................................20
3.1.4 Tool Knowledge Base..............................................................................20
3.1.5 Project Knowledge Base..........................................................................20
3.1.6 User Knowledge Base.............................................................................20
3.2 Data Flow........................................................................................................20
3.2.1 Endcap Cell Insertion...............................................................................25
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3.2.2 Global Constraints Generation.................................................................27
3.2.3 Clock Tree Insertion.................................................................................27
3.2.4 Filler Cell Insertion...................................................................................28
3.2.5 Special Net Routing.................................................................................29
3.2.6 Signal Routing .........................................................................................29
3.2.7 Parasitic Extraction..................................................................................32
3.2.8 Static Timing Analysis..............................................................................32
3.2.9 Signal Integrity Analysis...........................................................................32
3.2.10 Signal Integrity Repair..........................................................................33
3.2.11 DFII Generation....................................................................................34
3.2.12 Physical Verification.............................................................................34
CHAPTER 4. IMPLEMENTATION.............................................................................35
4.1 The Default Data and Flow Control.................................................................35
4.1.1 The Corporate Environment for Default Data Control..............................35
4.2 The MakeBlock Environment for Data and Flow Control ................................36
4.3 Information and Code Hierarchy.....................................................................37
4.3.1 The Utilities Namespace..........................................................................38
4.3.2 The Top Level Namespace......................................................................39
4.3.3 The Module Namespace..........................................................................40
4.3.4 Project and Block Namespace.................................................................41
4.4 Execution........................................................................................................42
4.4.1 MakeBlock Level Execution.....................................................................42
4.5 Reporting and Logging....................................................................................43
4.5.1 Messaging ...............................................................................................44
4.5.2 MakeBlock Log File .................................................................................44
4.5.3 Subtask Log File......................................................................................45
4.6 Extending Functionality...................................................................................46
4.7 API and TCL Extensions.................................................................................47
4.7.1 TCL Extensions .......................................................................................48
4.8 Supporting Implementation.............................................................................49
4.8.1 DFII Environment Tools...........................................................................49
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4.8.2 Technology Implementation.....................................................................54
CHAPTER 5. EXPERIMENTAL TESTING AND VALIDATION..................................63
5.1 Choosing Test Case - nnARM Core................................................................64
5.2 ARM7 Organization and Architecture..............................................................66
5.3 ARM7 Instruction Set......................................................................................66
5.4 Test Case Preparation....................................................................................67
5.4.1 Design Synthesis.....................................................................................67
5.4.2 Floor Plan Design....................................................................................68
5.4.3 Timing Constraints...................................................................................70
5.5 Design Hardening...........................................................................................71
5.6 Final Results...................................................................................................73
5.6.1 Stdout Output...........................................................................................73
5.6.2 HTML Output...........................................................................................81
5.7 Design Optimization........................................................................................83
5.7.1 Design Optimization Setup......................................................................83
5.7.2 Design Optimization Results....................................................................84
5.7.3 Optimized Design Results........................................................................90
CHAPTER 6. CONCLUSIONS...................................................................................95
6.1 Reduced Design Cycle Time...........................................................................95
6.2 Improved Design Parameters and Performance.............................................95
BIBLIOGRAPHY ...........................................................................................................97
VITA..............................................................................................................................99

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Table of Figures

Figure 1: ASIC Design Cycle...........................................................................................2
Figure 2: WLM vs Physical Synthesis.............................................................................5
Figure 3: Current ASIC Design Cycle..............................................................................6
Figure 4: MakeBlock Architecture .................................................................................18
Figure 5a: MakeBlock Default Data Flow......................................................................21
Figure 6: Full Floorplan.................................................................................................25
Figure 7: Endcap Cells..................................................................................................26
Figure 8: Paths not Covered by SDF.............................................................................27
Figure 9: Filler Cells, Power Rails and Routed Signals.................................................28
Figure 10: Antenna and Layer Hopping Diagram..........................................................30
Figure 11: SI Functional Failure [10].............................................................................33
Figure 12: SI Effect on Signal Delay [10].......................................................................33
Figure 13: MakeBlock Top-Level Log File.....................................................................45
Figure 14: Siggen Module Default Log File...................................................................46
Figure 15: Abstract Generator Compliance Checker.....................................................50
Figure 17: Connectivity Addition Form..........................................................................52
Figure 18: DEFin Repair Form......................................................................................54
Figure 19: Met1-Met2 Contact Pcell..............................................................................55
Figure 20: Met1-Met2 Contact P-cell Properties Form..................................................56
Figure 21: Power/Ground Bus Connections..................................................................58
Figure 22: Non-Default Rule Via Contacts....................................................................60
Figure 23: Default Via Contact......................................................................................61
Figure 24: ARM7 Organization and Architecture [23]....................................................66
Figure 25: ARM7 Instruction Set Quick Reference Guide [23]......................................67
Figure 26: nnARM Core Floor plan Initialization Form..................................................69
Figure 27: nnARM Core Floorplan ...............................................................................70
Figure 28: nnARM Core MakeBlock Top-Level Log File..............................................81
Figure 29: nnARM Core Ctgen Report.........................................................................82
Figure 30: nnARM Core Detailed Clock Timing Report................................................83
Figure 31: External Wrapper for Launching MakeBlock Runs.......................................84
Figure 32: Design Optimization Results – 70% Utilization............................................85
Figure 33: Design Optimization Results – 80% Utilization............................................85
Figure 34: Design Optimization Results - 85% Utilization............................................86
Figure 35: Design Optimization Results - 91% Utilization............................................86
Figure 36: Design Optimization Results - 92% Utilization............................................87
Figure 37: Design Optimization Results - 93% Utilization............................................87
Figure 38: Design Optimization Results - 94% Utilization............................................88
Figure 39: Design Optimization Results – 95% Utilization............................................88
Figure 40: Physical Placement Summary at 94% Utilization........................................89
Figure 41: Clock Tree Insertion Failure Summary........................................................89
Figure 42: Failed Physical Placement Summary at 95% Utilization.............................89
Figure 43: Failed Physical Placement Detailed Log at 95% Utilization.........................90
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Figure 44: Optimized Design Placed Layout.................................................................91
Figure 45: Optimized Design Clock Tree Layout...........................................................92
Figure 46: Optimized Design Routed Signal Layout......................................................93
Figure 47: Signal Routing Report for 70% Utilization...................................................94
Figure 48: Signal Routing Report for 93% Utilization...................................................94

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CHAPTER 1. INTRODUCTION
1.1 Background
The Very Large Scale Integrated (VLSI) Circuit industry for many years
has been using automation and Place-and-Route tools for development
and verification of Application Specific Integrated Circuits (ASICs). This
process is commonly referred to as RTL (Register Transfer Level) to GDS
(Graphic Design Station file format) flow, which is used to take a design
described in Hardware Description Language (HDL), such as Verilog or
VHDL, and turn it into functional silicon. As design complexity increased
as did the need to shorten design cycle time and achieve first pass
functional silicon, “RTL to GDS” flow went through various changes and
modifications [1, 2].
The high level basic flow consists of HDL development and its synthesis
into gate level netlist, followed by floorplan design and cell placement,
clock tree insertion, routing, signal integrity correction and finally timing
and physical verification as shown in Figure 1.
1