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About An Improved Design of A Fault Tolerant Reversible Binary Parallel Multiplier
The document summarizes reversible logic and fault tolerant reversible logic gates. It discusses how reversible logic circuits avoid energy loss during computation. Basic reversible gates like the Feynman gate, Peres gate, and Toffoli gate are described. Parity preserving reversible gates that enable fault tolerance are also covered, including the Feynman Double gate, Fredkin gate, and IG gate. The document aims to provide an overview of reversible logic and fault tolerant reversible logic gates as the foundation for presenting a new fault tolerant reversible binary parallel multiplier design.
Detailed Information
| Author: | ['erpublication'] |
|---|---|
| Publication Year: | 2017 |
| Pages: | 5 |
| Language: | English |
| Format: | |
| Price: | FREE |
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