Alternative gate designs for improved radiation hardness in bulk CMOS integrated circuits

296 Pages·1997·15.7 MB·English

by  Noe, Sidney Scott

NPS ARCHIVE
1997.03
NOE, S.
NAVAL POSTGRADUATE SCHOOL
Monterey, California
THESIS
ALTERNATIVE GATE DESIGNS FOR IMPROVED
RADIATION HARDNESS IN BULK CMOS
INTEGRATED CIRCUITS
by
Sidney ScottNoe
March 1997
Thesis Advisor: Douglas J. Fouts
Approvedfor public release; distribution is unlimited.
JORARY
DiJATE SCHOOL
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1. AGENCY USEONLY (Leave blank) 2. REPORTDATE REPORTTYPEAND DATES COVERED
March 1997 Master's Thesis
TITLEAND SUBTITLE FUNDINGNUMBERS
ALTERNATIVE GATE DESIGNS FOR IMPROVED
RADIATION HARDNESS IN BULK CMOS INTEGRATED
CIRCUITS
6. AUTHOR(S) Sidney ScottNoe
PERFORMINGORGANIZATIONNAME(S)ANDADDRESS(ES) PERFORMING
7.
Naval Postgraduate School ORGANIZATION
Monterey CA 93943-5000 REPORTNUMBER
9. SPONSORING/MONITORINGAGENCYNAME(S)AND ADDRESS(ES) 10. SPONSORING/MONITORING
DepartmentofDefense AGENCYREPORTNUMBER
9800 Savage Road
FortMeade, Maryland 20755-6000
11. SUPPLEMENTARYNOTES The views expressed in this thesis are those ofthe author and do not reflectthe
official policy orposition ofthe Department ofDefense orthe U.S. Government.
12a. DISTRIBUTION/AVAILABILITY STATEMENT 12b. DISTRIBUTION CODE
Approved forpublic release; distribution is unlimited.
13. ABSTRACT (maximum200words)
In the last 30 years, the world has become increasingly dependent on space-based systems.
These systems require varying degrees ofradiation tolerance to perform their missions. Current
radiation hardening processes for integrated circuits are expensive and consume significant layout area,
increase power consumption, and decrease the frequency ofoperation. Furthermore, it is becoming
more difficult to find fabricators for radiation-hardened electronic devices. In this thesis, two new
CMOS
transistor designs using a bulk process are tested for radiation hardness and are compared to a
standard design. Both show a degree ofimprovement in subthreshold leakage current and threshold
voltage shift over the control transistors. The new designs demonstrate an ability to reduce the effects
ofradiation on transistor parameters by means ofan applied voltage to a second layer ofpolysilicon
material above the control gate material.
14. SUBJECTTERMS CMOS, radiation, hardening, integrated circuits, VLSI 15. NUMBEROF
PAGES 249
16. PRICECODE
17. SECURITYCLASSIFICA- 18. SECURITY CLASSIFI- 19. SECURITY CLASSIFICA- 20. LIMITATIONOF
TION OF REPORT CATION OFTHIS PAGE TIONOFABSTRACT ABSTRACT
Unclassified Unclassified Unclassified UL
NSN 7540-01-280-5500 Standard Form298 (Rev. 2-89)
PrescribedbyANSIStd.239-18298-102
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Approved forpublic release; distribution is unlimited
ALTERNATIVE GATE DESIGNS FOR IMPROVED RADIATION
HARDNESS IN BULK CMOS INTEGRATED CIRCUITS
Sidney ScottNoe
Lieutenant, United States Navy
B.S., Rochester Institute ofTechnology, 1989
Submitted in partial fulfillment ofthe
requirements for the degree of
MASTER OF SCIENCE IN ELECTRICAL ENGINEERING
from the
NAVAL POSTGRADUATE SCHOOL
March 1997
Aecvvwe
tops
DUDLEY KNOX LIBRARY
NAVAL POSTGRADUATE SCHOOL
MONTEREY CA 93943-5101
ABSTRACT
In the last 30 years, the world has become increasingly dependent on space-based
systems. These systems require varying degrees ofradiation tolerance to perform their
missions. Current radiation hardening processes for integrated circuits are expensive and
consume significant layout area, increase power consumption, and decrease the frequency
ofoperation. Furthermore, it is becoming more difficult to find fabricators for radiation-
hardened electronic devices. In this thesis, two new transistor designs using a bulk
CMOS
process are tested for radiation hardness and are compared to a standard design.
Both show a degree ofimprovement in subthreshold leakage current and threshold
voltage shift over the control transistors. The new designs demonstrate an ability to
reduce the effects ofradiation on transistor parameters by means of an applied voltage to
a second layer ofpolysilicon material above the control gate material.
VI
..
TABLE OF CONTENTS
INTRODUCTION
I. 1
n. RADIATION EFFECTS 3
A. IONIZING RADIATION 3
1 Ionization Particles 4
2. Charge Trapping 5
3. Total Dose Effects 6
4. Dose Rate Effects 9
B. SINGLE EVENT EFFECTS (SEEs) 11
Single Event Upset 12
1
2. Single Event Latch-Up 12
IE. EXPERIMENTAL TRANSISTORS 17
A. CHIP ONE PART #N69P AP 17
1. Structure #1 17
2. Structure #2 18
3. Structure #3 18
B. CHIP TWO PART #N69P BP 18
1. Structure #1 18
2. Structure #2 19
3. Structure #3 19
IV. TESTING 21
A. INITIAL TESTING 21
vii
.
B. RADIATION DOSES 22
DATA COLLECTED
C. 23
V. RESULTS 25
STRUCTURE ONE
A. 25
1. NFETs 25
2. PFETs 27
STRUCTURE TWO
B. 28
NFETs 28
1.
2. PFETs 29
CONCLUSIONS AND RECOMMENDATIONS FOR FURTHER STUDY
VI. .... 31
A. DEVICE PARAMETER COMPENSATION 31
1 Structure One 31
2. Structure Two 33
B. RADIATION TOLERANCE 33
C. RECOMMENDATIONS FOR FURTHER STUDY 34
APPENDIX A. MOSIS FABRICATION LOT AVERAGE PARAMETRIC TEST
RESULTS 37
APPENDIX B. TEST CHIP DESIGN LAYOUTS 45
APPENDIX C. TESTING RESULTS 89
LIST OF REFERENCES 233
INITIAL DISTRIBUTION LIST 237
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