Table Of ContentAdvanced Test Methods for SRAMs
· · ·
Alberto Bosio Luigi Dilillo Patrick Girard
·
Serge Pravossoudovitch Arnaud Virazel
Advanced Test Methods
for SRAMs
Effective Solutions for Dynamic Fault
Detection in Nanoscaled Technologies
123
AlbertoBosio LuigiDilillo
LIRMM-Laboratoired’Informatiquede LIRMM-Laboratoired’Informatiquede
RobotiquedeMicroélectroniquede RobotiquedeMicroélectroniquede
Montpellier Montpellier
161RueAda 161RueAda
34392Montpellier 34392Montpellier
France France
[email protected] [email protected]
PatrickGirard SergePravossoudovitch
LIRMM-Laboratoired’Informatiquede LIRMM-Laboratoired’Informatiquede
RobotiquedeMicroélectroniquede RobotiquedeMicroélectroniquede
Montpellier
Montpellier
161RueAda
161RueAda
34392Montpellier
34392Montpellier France
France [email protected]
[email protected]
ArnaudVirazel
LIRMM-Laboratoired’Informatiquede
RobotiquedeMicroélectroniquede
Montpellier
161RueAda
34392Montpellier
France
[email protected]
ISBN978-1-4419-0937-4 e-ISBN978-1-4419-0938-1
DOI10.1007/978-1-4419-0938-1
SpringerNewYorkDordrechtHeidelbergLondon
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Acknowledgements
TheauthorswouldliketoacknowledgeStefanoDiCarlofromPolitecnicodiTorino,
Italy,forhismeaningfulhelpandsuggestionsafterreadingpartofthefirstdraftof
the book. Many thanks go to Alexandre Ney who did his PhD on memory test-
ing and diagnosis at LIRMM and provided part of the material reported in this
book.TheauthorsalsowishtothankJean-ChristopheVial,MagaliBastian,Simone
Borri,VincentGouin,andNabilBadereddine,fromInfineonTechnologies,Sophia
Antipolis,France,forthelong-termandfruitfulcooperationwiththeauthorsinthe
fieldofSRAMmemorytesting.
v
Advanced Test Solutions for Dynamic Faults
in SRAM Memories
Authorsofthebook:
AlbertoBosio,AssociateProfessor,LIRMM/UniversityofMontpellier–France
LuigiDilillo,CNRSResearcher,LIRMM/CNRS–France
PatrickGirard,CNRSResearchDirector,LIRMM/CNRS–France
SergePravossoudovitch,Professor,LIRMM/UniversityofMontpellier–France
Arnaud Virazel, Associate Professor, LIRMM/University of Montpellier –
France
Summaryandobjectiveofthebook:
Memorydesignandtestrepresentveryimportantissues.Memoriesaredesignedto
exploit the technology limits to reach the highest storage density and high speed
access.Themainconsequenceisthatmemorydevicesarestatisticallymorelikely
tobeaffectedbymanufacturingdefects.ThechallengeoftestingSRAMmemories
consists in providing realistic fault models and test solutions with minimal appli-
cation time. Due to the complexity of the memory device, fault modeling is not
trivial. Classical memory test solutions cover the so-called ‘static faults’ (such as
stuck-at, transition, and coupling faults) but are not sufficient to cover faults that
haveemergedinlatestVDSMtechnologiesandwhicharereferredtoas‘dynamic
faults’.
This book represents a valuable introduction and guide to new test approaches
developedsofarfordealingwithdynamicfaultsinthelatestgenerationofSRAM
memories.Thebookisorganizedinabottom-upapproach,startingfromthestudy
oftheelectricalcausesofthemalfunctionsuptothegenerationofsmartteststrate-
gies and dedicated algorithms. Based on this scheme, an exhaustive analysis of
resistive-open defects is first performed on each memory component (core-cells,
address decoders, write drivers, sense amplifiers, etc.) and the resulting dynamic
faultmodelsandrelatedtestsolutionsareenumerated.Diagnosisofdynamicfaults,
as wellasprocess variations and leakage currentinSRAMs,arealsoaddressed at
theendofthebook.
vii
Contents
1 BasicsonSRAMTesting . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 OverviewofSemiconductorMemories . . . . . . . . . . . . . . 1
1.2 TypicalStructureofanSRAM . . . . . . . . . . . . . . . . . . 3
1.3 TheContextofSRAMTesting . . . . . . . . . . . . . . . . . . 5
1.3.1 MemoryModel . . . . . . . . . . . . . . . . . . . . . . 6
1.3.2 FaultModelRepresentation . . . . . . . . . . . . . . . . 7
1.3.3 FaultModelClassification . . . . . . . . . . . . . . . . . 8
1.3.4 TestSolutionsandAlgorithms . . . . . . . . . . . . . . . 12
1.4 TestGeneration . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.5 TestValidation . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2 Resistive-OpenDefectsinCore-Cells . . . . . . . . . . . . . . . . . 21
2.1 TheSRAMCore-Cell . . . . . . . . . . . . . . . . . . . . . . . 21
2.1.1 ReadingintheCore-Cell . . . . . . . . . . . . . . . . . 21
2.1.2 WritingintheCore-Cell . . . . . . . . . . . . . . . . . . 22
2.2 AnalysisofResistive-OpenDefectsintheCore-Cell . . . . . . . 23
2.2.1 DefectLocation . . . . . . . . . . . . . . . . . . . . . . 23
2.2.2 DefectIncidenceAnalysis . . . . . . . . . . . . . . . . . 23
2.2.3 SimulationSet-UpandResults . . . . . . . . . . . . . . 26
2.3 AnalysisandTestofdRDF . . . . . . . . . . . . . . . . . . . . 27
2.3.1 FunctionalFaultModelingofdRDF. . . . . . . . . . . . 28
2.3.2 RES:ReadEquivalentStress . . . . . . . . . . . . . . . 29
2.3.3 MarchTestSolutionsDetectingdRDFs . . . . . . . . . . 33
2.4 AnalysisandTestofdDRF . . . . . . . . . . . . . . . . . . . . 37
2.4.1 FunctionalFaultModelingofdDRF. . . . . . . . . . . . 37
2.4.2 Experiments . . . . . . . . . . . . . . . . . . . . . . . . 38
2.4.3 MarchTestSolutionDetectingdDRFs . . . . . . . . . . 43
2.5 ImpactofTechnologyScaling . . . . . . . . . . . . . . . . . . . 45
2.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3 Resistive-OpenDefectsinPre-chargeCircuits . . . . . . . . . . . . 49
3.1 TheSRAMPre-chargeCircuit. . . . . . . . . . . . . . . . . . . 49
3.2 AnalysisofResistive-OpenDefectsinthePre-chargeCircuit . . 51
ix
x Contents
3.2.1 DefectLocation . . . . . . . . . . . . . . . . . . . . . . 51
3.2.2 DefectIncidenceAnalysis . . . . . . . . . . . . . . . . . 52
3.2.3 SimulationSet-UpandResults . . . . . . . . . . . . . . 53
3.3 AnalysisandTestofURRFandURWF . . . . . . . . . . . . . . 54
3.3.1 FunctionalFaultModelingofURRFandURWF . . . . . 54
3.3.2 Experiments . . . . . . . . . . . . . . . . . . . . . . . . 55
3.3.3 MarchTestSolutionsDetectingURWFs . . . . . . . . . 60
3.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4 Resistive-OpenDefectsinAddressDecoders . . . . . . . . . . . . . 65
4.1 TheSRAMAddressDecoder . . . . . . . . . . . . . . . . . . . 65
4.2 AnalysisofResistive-OpenDefectsintheAddressDecoder . . . 67
4.3 AnalysisandTestofADOF . . . . . . . . . . . . . . . . . . . . 67
4.3.1 FunctionalFaultModelingofADOF . . . . . . . . . . . 68
4.3.2 Experiments . . . . . . . . . . . . . . . . . . . . . . . . 70
4.3.3 MarchTestSolutionDetectingADOFs . . . . . . . . . . 75
4.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5 Resistive-OpenDefectsinWriteDrivers . . . . . . . . . . . . . . . 81
5.1 TheSRAMWriteDriver. . . . . . . . . . . . . . . . . . . . . . 81
5.1.1 WriteDriverWithintheI/OCircuitry . . . . . . . . . . . 81
5.1.2 OperationModeoftheWriteDriver. . . . . . . . . . . . 82
5.2 AnalysisofResistive-OpenDefectsintheWriteDriver . . . . . 84
5.2.1 DefectLocation . . . . . . . . . . . . . . . . . . . . . . 84
5.2.2 DefectIncidenceAnalysis . . . . . . . . . . . . . . . . . 85
5.2.3 SimulationSet-UpandResults . . . . . . . . . . . . . . 86
5.3 AnalysisandTestofSWDF . . . . . . . . . . . . . . . . . . . . 87
5.3.1 FunctionalFaultModelingofSWDF . . . . . . . . . . . 87
5.3.2 Experiments . . . . . . . . . . . . . . . . . . . . . . . . 88
5.3.3 MarchTestSolutionDetectingSWDFs . . . . . . . . . . 90
5.4 AnalysisandTestofURWF/URDWF . . . . . . . . . . . . . . . 92
5.4.1 FunctionalFaultModelingofURDWF . . . . . . . . . . 92
5.4.2 Experiments . . . . . . . . . . . . . . . . . . . . . . . . 93
5.4.3 MarchTestSolutionDetectingURDWFs . . . . . . . . . 96
5.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6 Resistive-OpenDefectsinSenseAmplifiers . . . . . . . . . . . . . 99
6.1 TheSRAMSenseAmplifier . . . . . . . . . . . . . . . . . . . . 99
6.1.1 SenseAmplifierWithintheI/OCircuitry . . . . . . . . . 99
6.1.2 OperationModeoftheSenseAmplifier . . . . . . . . . . 99
6.2 AnalysisofResistive-OpenDefectsintheSenseAmplifier. . . . 102
6.2.1 DefectLocation . . . . . . . . . . . . . . . . . . . . . . 103
6.2.2 DefectIncidenceAnalysis . . . . . . . . . . . . . . . . . 103
6.2.3 SimulationSet-UpandResults . . . . . . . . . . . . . . 104
6.3 AnalysisandTestofd2cIRF1 . . . . . . . . . . . . . . . . . . . 105
6.3.1 FunctionalFaultModelingofd2cIRF1 . . . . . . . . . . 105
Contents xi
6.3.2 Experiments . . . . . . . . . . . . . . . . . . . . . . . . 106
6.3.3 MarchTestSolutionDetectingd2cIRF1s . . . . . . . . . 107
6.4 AnalysisandTestofd2cIRF2 . . . . . . . . . . . . . . . . . . . 110
6.4.1 FunctionalFaultModelingofd2cIRF2 . . . . . . . . . . 110
6.4.2 Experiments . . . . . . . . . . . . . . . . . . . . . . . . 111
6.4.3 MarchTestSolutionDetectingd2cIRF2s . . . . . . . . . 112
6.5 d2cIRF1vs.d2cIRF2 . . . . . . . . . . . . . . . . . . . . . . . 113
6.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
7 FaultsDuetoProcessVariationsinSRAMs . . . . . . . . . . . . . 115
7.1 InfluenceofThresholdVoltageDeviationsinSRAM
Core-Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
7.1.1 SimulationFlow . . . . . . . . . . . . . . . . . . . . . . 116
7.1.2 MismatchSensitivityDuringRead/WriteOperations . . . 116
7.1.3 V MismatchRelatedFaultModels . . . . . . . . . . . . 119
t
7.2 ImpactofLeakageCurrentofCore-CellPass-Transistors
ontheReadOperation . . . . . . . . . . . . . . . . . . . . . . . 122
7.2.1 AnalysisofSupplyVoltageVariations . . . . . . . . . . 127
7.2.2 AnalysisofTemperatureVariations . . . . . . . . . . . . 128
7.2.3 TestandDiagnosisofLRFs . . . . . . . . . . . . . . . . 128
7.3 ComplexReadFaultAnalysis . . . . . . . . . . . . . . . . . . . 130
7.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
8 DiagnosisandDesign-for-Diagnosis . . . . . . . . . . . . . . . . . . 133
8.1 DiagnosisMethods. . . . . . . . . . . . . . . . . . . . . . . . . 133
8.1.1 Cause–EffectApproach:Signature-BasedDiagnosis . . . 133
8.1.2 Effect–CauseApproach:History-BasedDiagnosis . . . . 137
8.2 Design-for-DiagnosisofWriteDrivers . . . . . . . . . . . . . . 150
8.2.1 RequirementsforFault-FreeOperationsofaWriteDriver 150
8.2.2 DescriptionoftheCurrent-BasedDfDSolution. . . . . . 152
8.2.3 DescriptionoftheVoltage-BasedDfDSolution. . . . . . 154
8.2.4 DiagnosisSequence . . . . . . . . . . . . . . . . . . . . 157
8.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
General Introduction
History
Aftertheeraofmemorytechnologyallowingacapacityofafewbytes(intheearly
1940s), magnetic-core memory became the dominant form of memory until the
invention of the transistor in the late 1970s. The memory technology has evolved
successfullysincethen,followingthetrendcharacterizedbytheMoore’slaw.
Nowadays,semiconductormemoriesarewidelyusedtostoreprogramsandhuge
volumeofdatainalmosteverydigitalsystem.Formanycurrentapplications(audio,
video, data processing), the system performance is strictly related to the number,
capacity (size), and speed of its embedded memory units. A steadily increasing
percentage of area in Integrated Circuits (ICs) and Systems-on-Chip (SoCs) is
thus dedicated to implement memory components. According to the International
Technology Roadmap for Semiconductors (ITRS) drawn by the Semiconductor
IndustryAssociation(SIA),memoriesoccupied20%ofanSOCareain1999,52%
in 2002, and are forecasted to occupy up to 94% of a typical SoC area by 2014
(ITRS007).
AsmemoriesrepresentasignificantpartoftypicalSoCs,anyimprovementinthe
design and manufacturing processes of memory devices has a straightforward and
significantimpactonnumerousfeaturessuchascost,yield,performance,andrelia-
bilityofthewholeSoC.Forthisreason,memorieshavehistoricallybeendesigned
to exploit the technology limits and hence achieve the highest storage density and
accessspeed.Themainconsequenceisthatmemorydevicesarestatisticallymore
likelytobeaffectedbymanufacturingdefectsandprocessvariations,andthusare
becoming the main detractor of the overall SoC yield. The development of effi-
cienttestsolutionsforthesedevices,thoughrepresentingadifficultandcostlytask,
is therefore mandatory. Moreover, because memories are used as test vehicles for
monitoringthemanufacturingprocessandimprovingitsyield,extractingadditional
diagnostic data to determine the causes of failures is also required in the testing
strategy.
xiii
xiv GeneralIntroduction
SRAMs
Withthe rapid growth in the requirement for semiconductor memories, there have
been a number of technologies and types of memory that have emerged, each one
havingitsownfieldofapplications.Adetaileddescriptionofalltypesofsemicon-
ductormemoriesisprovidedinChapter1ofthisbook.Amongthesevarioustypes
ofmemories,StaticRandomAccessMemories(SRAMs)arewidelyusedinembed-
ded and high-speed applications such as cache memories for processors. SRAMs
arevolatilememoriesthatofferlow-power consumption andinwhichany storage
location(core-cell)canberandomlyaccessedinthesameamountoftime.SRAMs
cannotretaindatawithoutpowerbutpermitdatatobereadfromorwrittenintothe
storagecore-cells.Theterm‘static’referstothestructureofthestoragecellwhich
istypicallymadeofsixtransistorsincurrenttechnologies.
TestofSRAMs
As any other type of memory device, SRAMs are subject to defects or variations
duringthemanufacturingprocess,andhencehavetobetestedefficiently.Thechal-
lenge of testing SRAMs consists in providing realistic fault models and practical
test solutions with minimal application time. Classical SRAM test solutions cover
theso-called‘staticfaults’,suchasstuck-at,transition,andcouplingfaults,which
requireatmostonereadorwriteoperationtobesensitized,andarebasedonspecific
testscalled‘March’tests.Anumberofbookshavebeenpublishedsofartopresent
anddiscussthetaxonomyofstaticfaultmodelsanddedicatedMarchtestsolutions
(Sharma 1997, Van de Goor 1998, Adams 2002, Hamdioui 2004). However, these
testsolutionsarenotsufficienttocoveranewtypeoffaultsthatareemerginginthe
latest nanometer technologies and that are a consequence of the shrinking geome-
tries.Thesenewfaults,referredtoas‘dynamicfaults’andintroducedinVandeGoor
and Al-Ars (2000), are sensitized by more than one read or write operations and
hencerequireelaboratecombinationsofoperations,databackground,andaddress-
ing sequences to be detected. Typically, these faults model electrical malfunctions
duetoresistivedefects(opensandbridges)orparametermismatches,andmayoccur
inthevariousblocsofanSRAMsuchasthecore-cellarray,theaddressdecoders,
thepre-chargecircuits,thesenseamplifiers,andthewritedrivers.
Organization oftheBook
This book presents a comprehensive state-of-the-artof fault models and dedicated
testanddiagnosticsolutionsforthenewclassofdynamicfaults.Itiscomplemen-
tarytotheabove-mentionedbooksdedicatedtostaticfaults.Thebookisorganized
in a uniform manner for each chapter and presented with a bottom-up approach –
fromthetransistorleveluptothelogicandalgorithmiclevels.Foreachblocofan
