Advanced Electronics: Strictly as per Requirements of the Gujarat Technological University (GTU)

248 Pages·2011·5.47 MB·English

by  K. Lal Kishore

Advanced Electronics
Subject Code: 141101
Customized as per the B.E. Semester-IV syllabus
requirements of the Gujarat Technological University
K. Lal Kishore
Dharma Raj Cheruku
Raj Kamal
Customized by:
Nikhil Mariwala
Lecturer
Department of Electronic and Communication Engineering
University Institute of Engineering and Technology
Kurukshetra University
Kurukshetra
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Copyright © 2011 Dorling Kindersley (India) Pvt. Ltd.
Licensees of Pearson Education in South Asia
No part of this eBook may be used or reproduced in any manner whatsoever without the
publisher’s prior written consent.
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reserves the right to remove any material present in this eBook at any time.
ISBN 9788131759561
eISBN 9789332506879
Head Office: A-8(A), Sector 62, Knowledge Boulevard, 7th Floor, NOIDA 201 309, India
Registered Office: 11 Local Shopping Centre, Panchsheel Park, New Delhi 110 017, India
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Contents
Syllabus x
1. Transistor at High Frequencies 1-1
1.1 Hybrid–pi Model of aCEE Transistor 1-2
1.1.1 Hybrid Π Conductances 1-3
1.1.2 The Hybrid Π Capacitances 1-5
1.2 Validity of Hybrid –pi Model 1-7
1.3 High-Frequency Current Gain 1-7
1.4 Variation of Hybrid Π-Parameter 1-8
1.5 Gain Bandwidth Product 1-9
1.6 CEE current Gain with Resistive Load 1-10
1.6.1 I nput and Output time Constants 1-12
1.6.2 E xpression for the Current Gain 1-13
1.6.3 F requency Response and Effect of R 1-14
L
1.6.4 Effect of R onfff 1-14
L HH
1.7 S ingle Stage CEE Transistor Amplifier Response 1-15
1.7.1 The Transfer Function 1-15
1.7.2 Conclusions 1-17
1.7.3 Approximate Analysis 1-18
1.8 E mitter Follower at High frequencies 1-20
1.8.1 Single Pole Solution 1-21
Summary 1-22
Questions 1-23
2. Multistage Amplifi ers 2-1
2.1 Classification of Amplifiers 2-2
2.2 Distortion in Amplifiers 2-6
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2.3 Multistage Amplifiers 2-7
2.4 F requency Response of an Amplifier 2-11
2.5 Bandwidth of a Cascaded Amplifier 2-14
2.6 E ffect of an Emitter Bypass Capacitor 2-15
2.7 Coupling Capacitor 2-16
2.8 H igh Frequency Response of Two Cascaded CE Transistor Stages 2-18
2.8.1 Nodal Equation 2-19
2.8.2 Transfer Gain 2-20
2.8.3 Poles & Zeros 2-20
Summary 2-21
Questions 2-22
3. Feedback Amplifi ers 3-1
3.1 Types of Amplifiers 3-2
3.2 Types of Distortion in Amplifiers 3-6
3.3 Feedback Concept 3-7
3.4 Negative Feedback in Amplifiers 3-7
3.5 Transfer Gain with Feedback 3-9
3.6 A dvantages and Disadvantages of Negative Feedback 3-12
3.7 E ffect of Feedback on Input and Output Impedances 3-15
3.8 M ethod of Analysis of a Feedback Amplifier 3-15
3.9 Voltage Series Feedback Amplifier 3-17
3.10 Current Series Feedback Amplifier 3-19
3.11 Current Shunt Feedback Amplifier 3-21
3.12 Voltage Shunt Feedback Amplifier 3-22
Summary 3-23
Questions 3-23
4. Stability and Oscillators 4-1
4.1 Effect of Negative Feedback on Bandwidth 4-2
4.1.1 Effect on Lower 3dB Frequency 4-2
4.1.2 Effect on the Upper 3dB Frequency 4-3
4.2 D ouble Pole Transfer Function with Feedback 4-5
4.2.1 Values of Q 4-8
min
4.2.2 Poles with Feedback 4-8
4.2.3 Root Locus 4-9
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Contents v
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4.3 Compensation 4-9
4.3.1 Methods of Compensation 4-10
4.3.2 Dominant Pole Compensation 4-10
4.4 Pole Zero Compensation 4-11
4.4.1 C omparison of Dominant Pole & Pole-Zero Compensation 4-13
4.5 Compensation by Modification of β-Network 4-13
4.6 Barkhausen Criterion 4-13
4.7 Phase-Shift Oscillator 4-17
4.8 Resonant Circuit Oscillator 4-20
4.9 Hartley and Colpitt Oscillators 4-22
4.10 Wien Bridge Oscillator 4-26
4.11 Crystal Oscillator 4-28
4.12 Amplitude and Frequency Stability 4-30
Summary 4-32
Question 4-33
5. Operational Amplifi ers 5-1
5.1 Introduction 5-3
5.2 Basic Amplifiers 5-4
5.3 Classification of Op-Amps 5-4
5.4 Symbol 5-4
5.4.1 Package 5-5
5.4.2 Identification Code 5-6
5.4.3 Temperature Ranges 5-6
5.4.4 Nomenclature 5-6
5.4.5 Power Supply Connections 5-8
5.4.6 OP-AMP 5-8
5.4.7 Differential Amplifier 5-8
5.4.8 E mitter-Coupled Differential Amplifier 5-10
5.5 IC Operational Amplifier 5-13
5.6 Error voltages and currents 5-14
5.6.1 Input Offset Voltage (VVV ) 5-15
io
5.6.2 Input Offset Current (III ) 5-15
io
5.6.3 Output Bias Current (III ) 5-16
B
5.6.4 Input Resistance (R) 5-16
i
5.6.5 Input Capacitance (C) 5-16
i
5.6.6 Input Offset Voltage Drift [VVV ] 5-16
io(drift)
5.6.7 I nput Offset Current Drift [I ] 5-16
io(drift)
5.6.8 Common Mode Rejection Ratio [CMRR ((cid:2)(cid:2))] 5-16
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5.6.9 P ower Supply Rejection Ratio (PSRR) 5-17
5.6.10 Slew Rate (SR) 5-17
5.6.11 Gain BW Product (((A BW) 5-18
vv
5.6.12 Offset Voltage Adjustment 5-18
5.7 Frequency Roll Off 5-19
5.7.1 Octave 5-19
5.7.2 Decade 5-19
5.8 OP-AMP in Open-Loop Configuration 5-19
5.9 OP-AMP Going to Saturation 5-20
5.10 Virtual Ground 5-21
5.11 OP-AMP: a Direct Coupled High Gain Amplifier 5-22
5.12 Inverting Amplifier 5-23
5.12.1 Ideal Case 5-23
5.12.2 Input Impedance 5-24
5.12.3 Non-ideal Case 5-24
5.12.4 Output Impedance 5-24
5.12.5 Ideal Case: Non-Inverting Amplifier 5-25
5.12.6 Input Impedance 5-25
5.12.7 Non-ideal Case: Input Impedance 5-26
5.12.8 Output Impedance 5-26
5.13 Basic Linear Circuits Using Op-Amps 5-26
5.13.1 Adder Circuit 5-27
5.13.2 Buffer Circuit 5-28
5.13.3 General Analysis of Op-Amp Circuits 5-28
5.14 Ideal OP-AMP as a Subtractor 5-30
5.15 IdealOP-AMP as an Integrator 5-30
5.16 IdealOP-AMP as a Differentiator 5-31
5.17 OP-AMP Design Techniques 5-31
5.17.1 Biasing Method 5-32
5.17.2 I mproved Version of Current Mirror Circuit 5-32
5.17.3 Active Loads 5-32
5.17.4 Level Shifting 5-34
5.17.5 Output Stage 5-34
5.18 Measurement of Op-Amp Parameters 5-35
5.18.1 M easurement of Offset Voltage and Current 5-35
5.18.2 Measurement of CMRR (((ρ) 5-36
5.18.3 M easurement of Open-loop Input and Output Impedances 5-37
5.19 Measurement of PSRRR 5-37
5.20 Measurement of Slew Rate 5-37
5.21 Measurement of Open-Loop Gain 5-37
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Contents vii
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5.22 Frequency Response 5-38
5.23 AC Parameters of OP-AMP 5-40
5.24 Converters and Comparators 5-43
5.24.1 Converters 5-43
5.24.2 Comparators 5-45
Summary 5-49
Questions 5-50
6. Logic Families 6-1
6.1 RTL, DTL, TTL Logic Gates 6-3
6.1.1 R esistor–Transistor Logic (RTL) 6-3
6.1.2 Diode–Transistor Logic (DTL) 6-6
6.1.3 T ransistor-Transistor Logic (TTL) 6-8
6.1.4 TTL other than NAND Gate 6-13
6.2 DCTL 6-13
6.3 Meanings of Speed, Propagation Delay, Operating Frequency, Power Dissipated
Per Gate, Supply Voltage Levels, Operational Voltage Levels that Define Logic
States 1 and 0 6-14
6.4 Speed, Propagation Delay, Operating Frequency, Power Dissipated Per Gate, Supply
Voltage Levels, Operational Voltage Levels that Define Logic States′1′ and′0′ for
Various Families of Gates 6-15
6.5 Examples 6-15
6.6 High Threshold Logic (HTL) 6-23
6.6.1 H TL Connections for the Output atFF 6-23
6.6.2 L ogic Operation for the Output at FF 6-23
Summary 6-25
Questions 6-25
7. Analog to Digital and Digital to Analog Converters 7-1
7.1 Introduction 7-3
7.2 D/A Converter 7-4
7.2.1 Weighted Resistor Network 7-4
7.2.2 R-2R Ladder Network 7-5
7.3 DAC with Memory 7-9
7.4 DAC Specifications 7-11
7.5 A/D Converters 7-11
7.5.1 D/A Multiplexing 7-12
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7.5.2 A/D Multiplexing 7-13
7.5.3 Mosfet as a Switch 7-14
7.6 Ramp Conversion: Counter-Ramp Conversion Technique
of ADC 7-14
7.7 B inary-Coded Resistance Network for Successive-Approximation
Type A/D Conversion 7-16
7.8 S imultaneous A/D Converters
(Flash Type) 7-16
7.8.1 Advantage 7-17
7.8.2 Disadvantages 7-17
7.9 G eneral Description of One Class of ADC 7-18
7.9.1 Limitations 7-19
7.10 Staircase Ramp DVM 7-19
7.11 Voltage-to-Time Conversion 7-21
7.12 S uccessive-Approximation Type ADC 7-21
7.13 Successive Approximation ADC 7-23
7.14 DVM Types 7-24
7.14.1 Specifications of DVMs (Typical Values) 7-25
7.15 Non-Integrating Type DVMs 7-25
7.15.1 Potentiometric Type 7-25
7.15.2 Servo Type DVM 7-25
7.16 Ramp Type DVM 7-26
7.17 Integrating Type DVM 7-26
7.18 V/T Conversion 7-28
7.18.1 Single Slope V/T Conversion 7-28
7.18.2 Limitations 7-29
7.19 V/T Converters for A/D Conversion 7-30
7.19.1 Disadvantages 7-30
7.20 V/F Converter 7-30
7.20.1 Advantages 7-31
7.21 Dual Slope Integrating TypeDVM 7-32
7.21.1 Advantage 7-34
7.21.2 Disadvantage 7-34
7.22 Specifications of ADCs 7-34
7.23 A utomatic Polarity Indication for DVMs 7-35
7.23.1 Auto Ranging 7-36
7.23.2 Typical Case 7-37
7.24 ADC Terminology 7-38
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Contents ix
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7.25 Comparison of ADCs 7-40
7.25.1 Advantages of V/F Converter (Integrating Type) 7-40
7.25.2 Disadvantages 7-41
7.25.3 V/T Converter 7-41
7.25.4 Simultaneous ADC 7-41
7.25.5 Successive Approximation ADC 7-42
7.26 Series Mode Rejection 7-42
7.27 Simultaneous A/D Conversion Using Tunnel Diodes 7-42
7.28 V/F Conversion: (Integrating Type ADC) 7-43
7.29 S/H Amplifiers in A/D Converters 7-44
Summary 7-45
Questions 7-46
Index I-1
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