Table Of ContentA GUIDE TO VHDL
Second Edition
A GUIDE TO VHDL
Second Edition
Stanley Mazor
and
Patricia Langstraat
Synopsys, Inc.
.
.,
~
Springer Science+Business Media, LLC
Library of Congress Cataloging-in-Publicatlon Data
Mazor, Stanley, 1941-
A guide to VHDL / Stanley Mazor and Patricia Langstraat. -- 2nd
ed.
p. cm.
Includes bibliographical references (p. ) and index.
ISBN 978-1-4613-6412-2 ISBN 978-1-4615-3216-3 (eBook)
DOI 10.1007/978-1-4615-3216-3
1. VHDL (Computer hardware description language) 1. Langstraat,
Patricia, 1945 - II. Title.
TK7885.7.M39 1993
621.39'2--dc20 93-23132
CIP
Copyright © 1993 by Springer Science+Business Media New York
Originally published by Kluwer Academic Publishers in 1993
Softcover reprint ofthe hardcover 2nd edition 1993
AII rights reserved. No part ofthis publication may be reproduced, stored in a retrieval
system or transmitted in any form or by any means, mechanical, photo-copying, record ing,
or otherwise, without the prior written permission of the publisher, Springer Science+
Business Media, LLC.
Prinled an acid-free pap er.
v
Contents
Preface ix
Primary Benefits of Using VHDL x
About This Book xi
Notation Conventions xiii
Acknowledgements xv
About the Authors xvii
Introduction xix
Top-Down Design xx
Simulation xxi
Logic Synthesis xxii
Programming xxii
Summary xxiii
1: VHDL Designs
1.1 Library 1-3
Compilation 1-3
Simulation 1-3
Using Library Units 1-3
Library in File System 1-4
1.2 Package 1-5
1.3 Entity 1-6
1.4 Architecture 1-8
Behavioral Style Architecture 1-10
Dataflow Style Architecture 1-12
Structural Style Architecture 1-13
Design Hierarchy 1-14
1.5 Configuration 1-15
2: Primitive Elements 1 + 1; i 2
2.1 Scalars and Array Literals 2-2
Character Literal 2-2
String Literal 2-3
Bit Literal 2-4
BiCVector 2-4
IEEE Standard Logic 2-5
Std_Logic_V ector 2-5
Boolean Literal 2-6
Real Literal 2-7
Integer Literal 2-8
Time (Physical Literal) 2-9
2.2 Names (Identifiers) 2-10
2.3 Object Declarations 2-11
Range Constraint 2-12
Constant Declaration 2-13
Signal Declaration 2-14
Variable Declaration 2-15
2.4 Expressions 2-16
Typing 2-16
Precedence 2-19
IEEE Std_Logic_V ector Arithmetic 2-20
New VHDL '92 Operators 2-20
Table of Contents
vi
3: Sequential Statements
3.1 PROCESS Statement 3-4
3.2 Variable Assignment Statement 3-5
3.3 Sequential Signal Assignment Statement 3-6
3.4 IF Statement 3-6
3.5 CASE Statement 3-8
3.6 LOOP Statement 3-10
3.7 NEXT Statement 3-11
3.8 EXIT Statement 3-12
3.9 WAIT Statement 3-12
3.10 ASSERT Statement 3-13
3.11 Subprograms 3-14
Functions 3-14
Procedures 3-17
4: Advanced Types
4.1 Extended Types 4-2
Enumerated Types 4-3
Qualified Expressions 4-5
Type Conversion 4-6
Scalar Subtypes 4-7
4.2 Composite Types -Arrays 4-8
Index Range Declaration 4-8
Array Assignment 4-9
Slice 4-9
Aggregate 4-10
Variable Indexes 4-11
Array Type Declaration 4-12
Multi-Dimensional Arrays 4-13
Array of Arrays 4-13
Unconstrained Array Type 4-14
Array Index Constraint 4-14
Array Subtype 4-14
4.3 Composite Types -Records 4-16
4.4 Alias Declaration 4-16
4.5 Predefined Types: Text and Lines 4-17
4.6 Access Types 4-19
5: Signals & Signal Assignments
5.1 Structural Signals in Netlisting 5-2
5.2 Process Communication 5-3
5.3 Process/Component Connection -Testbench 5-4
Ad Hoc 5-4
Algorithmic 5-4
Vector File 5-4
5.4 Signal Declaration 5-5
5.5 Entity Signal Port Declarations 5-6
5.6 Signal Assignment in a Process 5-7
5.7 Signal Delay 5-8
Zero Delay 5-9
5.8 Sequential Signal Assignment Hazards 5-11
5.9 Simulation Cycle 5-13
5.10 Simulation and WAIT Statements 5-15
5.11 Sensitivity List 5-16
Table of Contents
vii
6: Concurrent Statements
6.1 The Process 6-2
6.2 Concurrent Signal Assignments 6-3
6.3 Conditional Signal Assignments 6-4
6.4 Selected Signal Assignments 6-5
6.5 Concurrent Procedure Call 6-6
6.6 BLOCK Statements 6-7
Guarded Blocks 6-8
7: Structural VHDL
7.1 Component Instantiation Using Named Notation 7-3
7.2 Generate Statement 7-4
7.3 Hierarchy 7-7
Component Declarations 7-7
7.4 Configurations 7-9
Configuration in Architecture 7-9
Configuration Outside of an Architecture 7-10
Two Ways of Configuring 7-10
Configuration Options 7-11
Port Remapping 7-11
Default Configuration 7-12
Null Configuration 7-12
7.5 Generics 7-13
Generic Declaration 7-13
Generic Map in Component Instance 7-13
Generic Default in a Component Declaration 7-14
Generic Default in a Package 7-15
Mapping Generics in a Configuration 7-15
Behavioral Model with Generics 7-16
8: Packages & Libraries
8.1 Constant Declarations 8-2
8.2 Deferred Constants 8-2
8.3 Subprograms in Packages 8-3
8.4 Component Declarations 8-4
8.5 Selected Names 8-5
8.6 USE Statement 8-6
8.7 General Notes on Procedures in Packages 8-7
8.8 Typical Vendor Packages 8-7
8.9 IEEE Package 1164 8-8
9: Advanced Topics: Adding Apples &Oranges
9.1 Overloading 9-2
Subprogram Overloading 9-2
Argument Overloading 9-3
Operator Overloading 9-3
Overloading and Qualified Expressions 9-5
9.2 Resolution Functions and Multiple Drivers 9-6
Three-State Logic 9-6
Multiple Signal Drivers 9-7
Three-State Buffers 9-8
Resolution Function for Subtype 9-10
Resolution Functions in IEEE Package 1164 9-10
9.3 Symbolic Attributes 9-11
Multi-Range Array Attributes 9-12
Array length Attributes 9-12
Range Attributes 9-13
Type Attributes -Position Functions 9-14
Signal Attributes 9-15
Table of Contents
viii
10: VHDl & logic Synthesis
10.1 Synthesis-Ready Code 10-2
10.2 CASE Statement Synthesis 10-3
10.3 FOR Statement Synthesis 10-4
10.4 A 4-Bit Adder 10-5
10.5 Synthesis and the WAIT Statement 10-6
10.6 State Machines in VHDl 10-8
10.7 Predefined Attributes for Synthesis 10-11
Design Constraints 10-11
Enumeration Encoding 10-11
A: Reserved Words
B: Application Examples
B.1 Vending Drink Machine -Count Nickels B-2
B.2 Structural Description of a Design Entity B-4
B.3 Carry-look-Ahead Adder B-5
C: VHDl Structure & Syntax
C.1 Design Hierarchy C-2
Architectures C-2
Processes C-4
Subprograms C-5
Packages C-5
C.2 Concurrent Statements C-7
Block Statement C-8
Component Instantiation Statement C-9
Concurrent Assertion Statement C-10
Concurrent Procedure Call C-11
Concurrent Signal Assignment Statement C-12
Generate Statement C-13
Process Statement C-14
C.3 Sequential Statements C-15
Assertion Statement C-16
Case Statement C-17
Exit Statement C-18
If Statement C-19
loop Statement C-20
Next Statement C-21
Null Statement C-22
Procedure Call Statement C-23
Retum Statement C-24
Signal Assignment Statement C-25
Variable Assignment Statement C-26
Wait Statement C-27
C.4 Specifications C-28
Attribute Specification C-29
Configuration Specification C-30
C.5 Library & USE Clauses C-31
LIBRARY Clause C-32
USE Clause C-33
Table of Contents
ix
C.6 Declarations C-34
Alias Declaration C-35
Attribute Declaration C-36
Component Declaration C-37
Constant Declaration C-38
File Declaration C-39
Signal Declarations C-40
Subprogram Declaration C-41
Subprogram Body C-41
Subtype Declaration C-42
Type Declaration C-43
Variable Declaration C-44
C.7 Library Units C-45
Architecture Body C-46
Configuration Declaration C-47
Entity Declaration C-48
Package Body C-49
Package Declaration C-50
C.8 Predefined Attributes C-51
Array-Related Attributes C-52
Signal Attributes C-54
Type-Related Attributes C-55
New Attributes in VHDL 92 C-56
C.g Package STANDARD C-57
C.10 TEXTIO Package C-58
Index
Bibliography
xi
Preface
A Guide to VHDL is intended for the working engineer who needs to develop,
document, simulate, and synthesize a design using the VHDL language. It is
for system and chip designers who are working with VHDL CAD tools, and
who have some experience programming in Fortran, Pascal, or C and have
used a logic simulator.
This book includes a number of paper exercises and computer lab
experiments. If a compiler/simulator is available to the reader, then the lab
exercises included in the chapters can be run to reinforce the learning
experience. For practical purposes, this book keeps simulator-specific text to
a minimum, but does use the Synopsys VHDL Simulator command language
in a few cases.
The book can be used as a primer, since its contents are appropriate for an
introductory course in VHDL. We have taught the VHDL language with
approximately 1 hour per chapter (e.g. about 10 hours of lecture) and 15
hours of simulator exercises.
When the Department of Defense implemented their VHSIC project (yery
High Speed Integrated Circuit), the DOD also funded the VHDL project in
1983 - the VHSIC Hardware Description Language. In 1992 the DOD
embarked on a program called "Seven Thrusts" in which VHDL is identified
as a key technology.
Although hardware-description languages had been around for several
decades, they were overlooked during the last 10 to 15 years because of the
popularity of schematic-capture systems. Numerous books describe the
motivations and background of the language committee, which evolved the
language over several years.
The official adoption of VHDL by the IEEE (Standard 1076) in December,
1987 was a significant event in making VHDL an international and
recognized standard. The VHDL language was updated in 1992 with some
minor improvements. In most cases, the language is upward compatible.
Although this book is based primarily on the VHDL 1987 standard, we have
indicated the significant changes in the 1992 language to assist you in writing
upwardly compatible code.
xii
Preface
Primary Benefits of Using VHDL
• Makes the design specification more technology-independent:
- Uses multiple vendors
- Avoids part obsolescense
- Facilitates updating design
- Documents in a standard way
• Automates low-level design details:
- Reduces design time
- Gets to market quicker
- Reduces design cost
-Eliminates low-level errors
• Improves design quality:
- Explores alternatives
- Verifies functions at a higher level
- Verifies that implementation matches function
- Promotes design component re-use and sharing
