Table Of ContentReference Matlab code is available at sites.google.com/site/shahriarshahabuddin/matlab simulator
A Customized Lattice Reduction Multiprocessor for
MIMO Detection
Shahriar Shahabuddin, Janne Janhunen, Amanullah Ghazi
Zaheer Khan, and Markku Juntti Department of Computer Science and Engineering
Centre for Wireless Communications University of Oulu, Finland
University of Oulu, Finland Email: fi[email protected].fi
Email: fi[email protected].fi
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1 Abstract—Lattice reduction(LR) is a preprocessingtechnique There are several hardware accelerators proposed in [4]
0 for multiple-input multiple-output (MIMO) symbol detection to [5] [6] [7] for different LR algorithms. The fixed hardware
2 achieve better bit error-rate (BER) performance. In this paper, implementations provide high data rate and consume less
we propose a customized homogeneous multiprocessor for LR.
n silicon area compared to the customized application specific
The processor cores are based on transport triggered architec-
a ture (TTA). We propose some modification of the popular LR processors(ASIP).Thedrawbackofthefixedhardwareimple-
J
algorithm, Lenstra-Lenstra-Lova´sz (LLL) for high throughput. mentationisthatitoperatesonlyona fixedset ofparameters
7 The TTA cores are programmed with high level language. Each due to the hardwired control path and it is not possible to
1 TTA core consists of several special function units to accelerate
modify the control path in the future. An ASIP customized
] tahseinpgrloegmraamtricxodfoer.TLhRe.mThueltiaprrcohcietesscoturrteakisessy1n8t7hecsyiczleedsotonr9e0duncme for a small set of algorithms is an attractive solution in terms
T
technology and takes 405 kgates at 210 MHz. ofcost,siliconareaandhighthroughput.Mostimportantly,an
I ASIP reducesthe designrisk with an instructionmemorythat
.
s I. INTRODUCTION canbeusedtoloadnewprogramsorcontrolinstructions.The
c
[ Multiple-inputmultiple-output(MIMO)isakeytechnology control instructions can be easily obtained by a retargetable
to utilize the available radio spectrum efficiently. The basic compiler for that particular customized architecture.
1
idea of MIMO is to send multiple independent data streams Acustomizedverylonginstructionword(VLIW)processor
v
0 from multiple antennas in the same frequency band. These is implemented in [8] for the LR. We take different approach
6 independent streams need to be separated at the receiver to anddesignacustomizedmultiprocessorbasedonthetransport
8 identifythesymbolthatisbeingtransmittedbyusingaMIMO triggered architecture (TTA) paradigm. TTA is a processor
4
detector. Maximum likelihood (ML) is the optimal solution design philosophy where the programmer can control the
0
for the MIMO detection problem that compares the incoming internaldata transportsbetween differentfunctionunitsofthe
.
1 symbol with every possible symbols in the constellation. processor.TTA exploitsthe instructionlevelparallelism(ILP)
0
However, the ML algorithm is too complex for practical real- by processingseveralinstructionsin a single clockcycle. The
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1 timeimplementations.Lineardetectionispopularforpractical TTA based codesign environment (TCE) tool is used in this
: implementations. The linear MIMO detection algorithms are work to design the TTA processor cores. TCE enables the
v
lesscomplex,butsuffersfromadegradedbiterror-rate(BER) designer to write an application with a high level language
i
X performance. anddesignthe targetprocessorina graphicaluserinterfaceat
r Latticereduction(LR)isapreprocessingtechniquethatcan the same time. A turbo decoder and a MIMO detector design
a
be used with the linear detection to significantly improve the using TCE can be found in [9] and [10]. In this work, every
BER performance and reduce the gap between the traditional core of the proposed multiprocessor is programmed with C
linear detectors and optimal ML. LR transforms the MIMO language to shorten the time-to-market. The multiprocessor
channelmatrixtoanearorthogonalmatrixandthusfacilitates takes 187 cyclesand achievesa maximumclock frequencyof
to achieve a better BER performance. The most used LR 210MHz on 90nm technology.To our knowledge,this is the
algorithm is called the Lenstra-Lenstra-Lova´sz (LLL) algo- first TTA based customized architecture for LR.
rithm according to the name of the inventors [1]. The LLL
algorithm poses many challenges due to the undeterministic II. SYSTEMMODEL
executiontime and highercomputationalcomplexity.We pro-
A. Conventional MIMO Detection
pose a modified LLL (MLLL) algorithm that is based on the
original LLL algorithm on complex domain. We use a fixed ConsideraMIMOsystemconsistsofMT transmitantennas,
structurefortheLLLbasedon[2].InsteadofusingtheLova´sz whicharesendingdataoverthechannelandNR receiveanten-
condition, a less complex Siegel condition is applied [3]. An naswhicharereceivingtransmittedbitsfromthechannel.The
early termination technique is used as proposed in [4]. We modulation scheme that is used here is quadrature amplitude
demonstrate by Matlab simulation that the BER performance modulation (QAM) with the assumption N ≥ M . The
R T
loss of the hardware friendly MLLL algorithm is negligible. received signal y can be represented as
Reference Matlab code is available at sites.google.com/site/shahriarshahabuddin/matlab simulator
III. LATTICEREDUCTION ALGORITHM
y=Hx+n, (1)
LLL algorithm is widely used to compute the suitable
where y ∈ CNR is the received signal vector, x ∈ CMT is unimodular matrix T and to obtain a reduced lattice basis.
the transmit symbol vector, H ∈ CNR×MT is the channel LLL was originally proposed for the real valued LR [1].
matrix and n ∈ CNR is the circularly symmetric complex However, the channel matrix is naturally complex valued and
white Gaussian noise vector with zero mean and variance σ2. therefore, complex version of LLL (CLLL) is used to reduce
In the receiver, the linear zero forcing (ZF) detector cal- the complexity.
culates the inverse of the channel matrix to compute the The CLLL algorithm suffers from irregular dataflow,
transmitted symbol vector which can be expressed by, which eventually leads to higher latency. Therefore, a fixed-
complexity LLL (fcLLL) algorithm is proposed in [2]. The
x˜=(HHH)-1Hx=H†x. (2) fcLLL alters the signal flow of the CLLL to follow a deter-
ministic structure. It is possible to utilize less complex Siegel
where H is the channelmatrixand (·)† denotesthe pseudoin-
algorithm instead of the complex Lova´sz condition [3]. It is
verse.Typically,thechannelmatrixHisQRdecomposedinto
also very importantto use an early termination mechanism to
twopartsasH=QR.HereQ∈C(NR×NR)denotesaunitary
meet the strict requirements. Applying all this modifications,
matrixandR∈C(NR×NR)denotesanuppertriangularmatrix.
we propose a modified-LLL (MLLL) algorithm for LR with
B. Lattice Reduction less complexity and negligible BER performance loss. The
MLLLimplementedinthispaperissummarizedinAlgorithm
A lattice is a periodic arrangement of discrete points. A
1.
lattice can be characterized in terms of a set of basis vectors,
where any points of the lattice can be represented by a
Algorithm 1 Modified CLLL Algorithm (MLLL)
superposition of integer multiples of the basis vectors. For
simplicity, we call the set B=(b ,b ,....,b ) as the basis of INPUT: Q∈CNR×NR , R∈CNR×NR , δ
1 2 n
the lattice. 1: Initialization Q˜ :=Q , R˜ :=R , T:=IMT
A complex valued lattice in the n-dimensional complex 2: k :=2
space Cn can be defined as 3: while k ≤iterations
4: for l=k−1 to 1 step −1
L={υ|υ =Bω}, (3) 5: µ=R˜(l,k)/R˜(l,l)
6: if µ6=0
where B is the basis of the lattice and ω = [ω1,ω2,....,ωn]. 7: R˜(1:l,k):=R˜(1:l,k)−µR˜(1:l,l)
Note that in (3), the υ, ω and matrix B can be replaced with 8: T(:,k):=T(:,k)−µT(:,l)
y, x and H respectively to obtain L = {y|y = Hx}. In this 9: end
case, the vector space L is the set of all possible undisturbed 10: end
receivedsignalpoints.Therearemanybasesthatcanspanthe 11: if δR˜(k−1,k−1)2 >R˜(k,k)2
space L, and the aim of the LR algorithm is to find a set of 12: Swap columns k−1 and k in R˜ and T
least correlated base with the shortest basis vectors [11]. 13: Θ = α β with α = R˜(k−1,k−1) and
(cid:20)−β α(cid:21) kR˜(k−1:k,k−1)k
C. LR-based MIMO Detection
β = R˜(k,k−1)
LR finds an improved basis for the lattice induced by the kR˜(k−1:k,k−1)k
channel. The original basis and the reduced basis are related 14: R˜(k−1:k,k−1:k):=ΘR˜(k−1:k,k−1:k)
bya unimodularmatrix,T. Therefore,the LRaideddetection
finds the received symbol in the new reduced basis and 15: Q˜(:,k−1:k):=Q˜(:,k−1:k)ΘT
afterwards transfer the signal in the original lattice. The new 16: k :=max{k−1,2}
channel matrix after the LR can be expressed as, H˜ = HT 17: else
andthetransmittedsignalisalsotreatedasmultipliedbyT−1 18: k :=k+1
whichisz=T−1xforthereducedbasis. Thereceivedsignal 19: end
y=Hx+n can be expressed as 20: end
y=HTT−1x+n=H˜z+n. (4)
The BER performanceof the traditionalZF, originalCLLL
The LR aided detection operates on H˜ and z instead of H aided ZF, MLLL aided ZF and the optimal ML is simulated
and x. The LR aided ZF detector can be expressed as for various signal-to-noise (SNR) in a Matlab simulator. An
x˜=(H˜HH˜)-1H˜z=H˜†z. (5) additive white Gaussian noise (AWGN) channel is used for
16-QAM modulation and the BER is averaged over 10 000
The LR algorithm is applied on the QR decomposed H to Monte-Carlo trials. Fig. 1 shows the MLLL algorithm with 5
obtain the modified Q˜ and R˜. Afterwards, the lattice reduced iterations.Itcanbeseenthattheperformancelossisnegligible
channel matrix can be obtained as H˜ =Q˜R˜. compared to the original CLLL algorithm.
Reference Matlab code is available at sites.google.com/site/shahriarshahabuddin/matlab simulator
and 0 of the CORDIC with rotation mode, it is possible to
100
ZF calculate the cosine and sine values directly. Therefore, the
CLLL
MLLL (5 iterations) angle calculation done in a conventional CORDIC block is
ML
10−1 not needed here. In every stage it is possible to calculate the
values of the signums and add or subtract accordingly in the
R)
BE rotation mode. As we need a 16-bit CORDIC, there are two
bit error rate (10−2 oatanpkdteiosint1esr6at-otcelsdoec1sk6igcntyimciltee.ssAtonoviectreormtahtpeivuet1e-CstthOaegReoDudItCaptuattph.aaFtthou.rsHaesopwrreoegcvieessrt,seorisrt
10−3 basedimplementationa16-cycleSFUiscomplexastherewill
be 15 NOP operations in the assembly code. It is possible to
fully unroll the CORDIC block without any registers. Then
10−40 5 10 15 20 25 30 35 40 thecriticalpathforthe CORDICblockbecomestoohigh.We
average SNR per receive antenna [dB]
find a compromise between the two approach and design a
4-stage CORDIC datapath that can be reused four times to
Fig.1. BERpeformance ofMLLLalgorithm.
create a 4-cycle master-slave CORDIC. The blockdiagram of
the master-slave CORDIC is presented in Fig. 2, where the
IV. TTA MULTIPROCESSORFORMLLL ellipsecontainsasinglestageofthedatapath.AnARRANGE
SFU is designed to rearrange the 32-bit variables.
A. Special Function Units
Sixspecialfunctionunits(SFU)aredesignedandwrittenin
B. High Level Architecture of the multiprocessor
VHSIC hardware description language (VHDL) to accelerate
A32-bitfixedpointTTAprocessorisdesignedtosupporta
eachiterationof theMLLLalgorithm.A specialfunctionunit
single iteration of the MLLL algorithmand five of these TTA
is designed to support the complex multiplication (CMUL)
cores are connectedin a pipelined fashion to compute the LR
operation.Datalevelparallelism(DLP)isappliedinthedesign
matrix.PartofasingleTTAprocessorcoreisillustratedinside
by packing the 16-bit real part and 16-bit complex part in
thedottedblockofFig.3.Forreadability,thewholeprocessor
a 32-bit complex variable. Therefore, CMUL uses four 16-
isnotgiven.Theblocksintheupperpartofthecorerepresent
bit multipliers, a single 16-bit adder and 16-bit subtractor to
thefunctionunitsandregisterfilesoftheprocessor.Theblack
support the complex multiplication.
horizontal straight lines represent the buses of the processor.
TwoSFUsforµcalculationandsizereductionaredesigned
The vertical rectangular blocks represent the sockets.
according to [8]. These SFUs are single-cycle and multiplier-
less. It is observedfromthe Matlab simulationsthatthe value
of µ has a range of [−4,4], and thus, the dynamic range of
theSFUsaresetaccordingly.AnothersimpleSFUisdesigned
to compute the SIEGEL criterion. Instead of multiplying the
input with .75 the SIEGEL SFU calculates the value with a
combination of two shifters and one adder.
Fig.3. Themultiprocessor architecture.
Each core includes the load/store unit (LSU), arithmetic
logic unit (ALU), global control unit (GCU), register files,
several conventional function units and SFUs. The Q, R
and T matrix are read from three separate first-in-first-out
(FIFO) memory buffer by using the function units called
STREAM. The STREAM units can read every input sample
in one clock cycle. Three STREAM units are used to get the
inputs simultaneously. Three STREAM unit is used to write
Fig.2. 4-cyclecordicarchitecture. the outputs in the memory buffer.
Tenregisterfilesareusedtosavetheintermediateresults.A
The most complexSFU that lies in the datapath of a single singleBooleanregisterfileisincludedintheprocessordesign.
TTA core is the CORDIC SFU. A master-slave cordic is When the registers are not enough, the processor is able to
considered in this work [4]. The master-slave CORDIC is access the data memory to temporary store data through the
a combination of two CORDIC blocks in vectoring mode LSU. The SFUs can be called by macros to accelerate the
and rotation mode respectively. By setting the input as 1 program code.
Reference Matlab code is available at sites.google.com/site/shahriarshahabuddin/matlab simulator
Eightbusesareusedinasinglecoreandthereforethecoreis the instruction memory with new binary program image. The
abletoprocesseightinstructioninasingleclockcycle.Asthe updated binary instructions can be obtained by compiling the
datapathisexposedtotheprogrammerintheTTAarchitecture, other LLL algorithms for our particular architecture with the
it is possible to remove the unused or less frequently used help of a retargetable compiler.
connectionbetweenthefunctionunitsandbuses.Thus,several The programmable VLIW core [8] takes less clock cycle
connectionsof the processor is removed to reduce the cost of and flexible. The implementation consisted of not only LR,
a core. The connection between function units and buses is but also QR decomposition and detection also. However, it is
illustrated by black spots in the sockets of Fig. 3. notcleartheamountofareaneededonlyfortheLR.Thetotal
The cores are connected to one another by FIFO buffer area is very highcomparedto the other implementationseven
memories. In this way, five iteration of MLLL can be pro- at 40 nm technology.
cessed in parallel. The cores are identical and except the first
TABLEII
core, the rest of the cores use the same program image.
IMPLEMENTATIONCOMPARISON
V. RESULTS ANDDISCUSSION Reference Architecture/tech. area max-freq. cycles
[4] .13µm 107kGE 333MHz 14
ItcanbeseenfromtheTCEtoolthattheTTAmultiproces- [5] Virtex-IIPro N/A 100MHz 420
[6] .13µm 125kGE 352MHz 40
sortakes187cyclestocomputetheMLLLalgorithm.Someof [7] 90nm 200kGE 37MHz 5
[8] VLIW(40nm) 6364kGE 700MHz 21
the operations executed during a single iteration is presented
Proposed TTA(90nm) 405kGE 210MHz 187
in Table I. The conventional operations like addition, shifts
are not shown in the table.
VI. CONCLUSION
TABLEI WeproposeamodifiedLLLalgorithmforLR.Wesimulated
NUMBEROFOPERATIONS inMatlabtheperformanceofthealgorithmandproposeacus-
Operation No.ofOps tomized multiprocessor architecture for the MLLL. The cores
ARRANGE 18 areprogrammablewiththehelpofaretargetablecompiler.The
CORDIC 9
CMUL 72 flexible implementation shows great promise to support later
STREAM 84
SIEGEL 3 field updates and provides high throughput with a moderate
SIZEREDUCTION 34 cost.
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