6-9 GHz Low-Noise Amplifier Design and Implementation

108 Pages·2010·3.73 MB·English

by  Mohammad Billal Hossain

LiU-ITN-TEK- A --10/047--SE

6-9 GHz Low-Noise Amplifier

Design och Implementering

Mohammad B illal Hossain

2010-06-14

Department of Science and Technology Institutionen för teknik och naturvetenskap
Linköping University Linköpings Universitet
SE-601 74 Norrköping, Sweden 601 74 Norrköping
LiU-ITN-TEK-A--10/047--SE
6-9 GHz Low-Noise Amplifier
Design och Implementering
Examensarbete utfört i Electronics
vid Tekniska Högskolan vid
Linköpings universitet
Mohammad Billal Hossain
Handledare Adriana Serban
Examinator Adriana Serban
Norrköping 2010-06-14
Upphovsrätt
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© Mohammad Billal Hossain
6-9 GHz Low-Noise Amplifier Design and Implementation
Mohammad Billal Hossain
June 14, 2010
Preface
This report is the result of Master of Science Thesis carried out at the Department of
Science and Technology (ITN) in Linköping University.
I would like to take a chance to thank the people who have helped and encouraged
me during this Master Thesis work. First of all, I want to express my gratitude to
Adriana Serban, for giving me the opportunity to perform my Master Thesis at ITN
department and for being my supervisor. This thesis work could not have been
accomplished without her guidance and full assistance. I would also like to thank
professors in ITN department Shaofang Gong, Magnus Karlsson and Allan Huynh
for their suggestion and comments.
i
Abstract

Low-noise amplifier design (LNA) is a critical step when designing a receiver front-
end. For the broadband technologies and particularly ultra-wideband (UWB) system,
designing the LNA becomes more challenging. This master thesis mainly focuses on
the LNA design for the European UWB recommendation, i.e. LNA covering the 6 - 9
GHz spectrum. Moreover, better understandings of the design process in correlation
with the implementing of the LNA on a printed circuit board (PCB) were expected.
The LNA was manufactured, assembled and measured with network analyzer. This
report presents a complete functional design of an UWB LNA.
ii
List of Abbreviations
ADS Advanced Design System
BPFs Bandpass Filters
BW Bandwidth
CAD Computer Aided Design
EDA Electronic Design Automation
EMI Electromagnetic Interference
EIRP Equivalent Isotropically Radiated Power
FCC Federal Communication Commission
FM-UWB Frequency Modulation UWB
GaAs Gallium Arsenide
HBTs Hetero-junction Bipolar Transistors
HEMTs High Electron Mobility Transistors
JFETs Junction Field Effect Transistors
LNA Low-Noise Amplifier
MC-UWB Multi Carrier UWB
MW Microwave
NF Noise Figure
OFDM Orthogonal Frequency Division Multiplexing
PSD Power Spectral Densities
RF Radio Frequency
RFI Radio Frequency Interference
RFID Radio Frequency Identification
RSC Radio Spectrum Committee
SMDs Surface Mount Devices
S-parameters Scattering Parameters
UMTS Universal Mobile Telecommunication System
UWB Ultra-wideband
VSWR Voltage Standing Wave Ratio
WPAN Wireless Personal Area Network

iii
List of Figures
Figure 2- 1 Diagram of band allocation [7]
Figure 2- 2 FCC emission limit for outdoor UWB communications [3]
Figure 2- 3 FCC emission limit for indoor UWB communications [3]
Figure 2- 4 Spectrum of the Main Interfering Communication Standards for UWB
Communication System [11]
Figure 2- 5 Skin depth area of a wire [13].
Figure 2- 6 Electric equivalent circuit representation of the resistor [15].
Figure 2- 7 Absolute impedance value of a 500 ohm thin-film resistor as a function of
frequency [15].
Figure 2- 8 Electric equivalent circuit for a high frequency capacitor [15].
Figure 2- 9 Absolute value of the capacitor impedance as a function of frequency
[15].
Figure 2- 10 Distributed capacitance and series resistance in the inductor coil [4].
Figure 2- 11 Equivalent circuit model of the HF inductor [15].
Figure 2- 12 Frequency response of the impedance of an RFC [15].
Figure 2- 13 Biasing effect of n-channel JFET [21]
Figure 2- 14 IV characteristic of FET [23].
Figure 2- 15 GaAs MESFET [5]
Figure 2- 16 HEMT [16]
Figure 2- 17 High frequency FET model [22]
Figure 2- 18 Segment of transmission line expressed with distributed parameters R,
L, C and G, where all parameters are given in terms of unit length [4].
Figure 2- 19 Terminated transmission line at location z=0.
Figure 2- 20 (a) Microstrip line; (b) end view of microstrip line [9].
Figure 2- 21 Line voltages reference to the load end [21]
Figure 2- 22 Smith Chart.
Figure 2- 23 Parametric representation of the normalized resistance r [15].
Figure 2- 24 Parametric representation of the normalized reactance x [15].
Figure 2- 25 Smith chart by combining r and x circles for Γ ≤1[15].
Figure 2- 26 Reflection coefficient: A = (0.8-j1.6), angle BOC=-55.5 degree [21].
Figure 2- 27 T network connected to the base-emitter input impedance of a bipolar
transistor. AssumingZ =50 ohm and f =2 GHz [15]
0 c
Figure 2- 28 Computation of the normalized input impedance of the T network
Figure 2- 29 Two-port network [15].
Figure 2- 30 Two port scattering network with source and load [21]
Figure 3- 1 RF receiver using a heterodyne architecture [5].
Figure 3- 2 Thermal noise [7]
Figure 3- 3 Shot noise [7]
Figure 3- 4 Representation of noise by input noise generators [7].
Figure 3- 5 Simplified single stage amplifier [3]
Figure 3- 6 Eight possible two components networks [3].
Figure 3- 7 Impedance effects of series and shunt connections of L and C [3].
Figure 4- 1 Minimum noise figure, associated gain vs. frequency characteristics [3].
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Figure 4- 2 ADS Simulation setup for the I-V characteristic using electrical model of
NE3512S02.
Figure 4- 3 Simulated I-V Characteristic of NE3512S02.
Figure 4- 4 I-V Characteristic of NE3512S02 according to data sheet [3]
Figure 4- 5 Simulation setup for the Electrical and S-Parameter model of
NE3512S02.
Figure 4- 6 S-Parameters are estimated using Electrical (Thick line) and S-Parameter
model (Thin line) at the Q-point (I = 20 mA and V = 2 V).
D DS
Figure 4- 7 Fixed-bias Configuration [7]
Figure 4- 8 Self-bias Configuration [7]
Figure 4- 9 Active-bias Configuration [8].
Figure 4- 10 Layout component of footprint for the transistor (NE3512S02) and three
types of packages such as 0402, 0603 and 0805.
Figure 4- 11 Different layout components of via hole model and ADS via model.
Figure 4- 12 ADS set-up for via simulation.
Figure 4- 13 Reflection coefficients for different via models.
Figure 4- 14 Impedance vs Frequency. Solid line represents for ATC100A101
(100pF) and dot line for ideal 100 pF capacitor [11] .Figure 4- 14 Impedance vs
Frequency. Solid line represents for ATC100A101 (100pF) and dot line for ideal 100
pF capacitor [11] .
Figure 4- 15 Insertion loss (S21) of ATC100A101 (100 pF) capacitor [11].
Figure 4- 16 Kemet COG ceramic capacitor model schematic [12].
Figure 4- 17 Kemet X7R ceramic capacitor model schematic [12].
Figure 4- 18 Murata Monolithic ceramic SMT Capacitor model [12].
Figure 4- 19 CAPP2 (Chip capacitor) model for ATC [12].
Figure 4- 20 Forward transmission vs frequency characteristics for 1 pF capacitor
dofferent companies such as Kemet, ATC, Philips and Murata.
Figure 4- 21 Forward Transmission vs Frequency characteristic of Kemet capacitor
model with different values.
Figure 4- 22 Forward Transmission vs Frequency for Bypassing Kemet capacitor
model. Thick line for C1 and thin line for C2 to C4
Figure 4- 23 Three types of RF choke [13].
Figure 4- 24 ADS set-up for RF choke using quarter wave stub.
Figure 4- 25 RF choke using radial stub.
Figure 4- 26 RF choke using butterfly stub.
Figure 4- 27 Forward transmission vs frequency characteristics of different types of
RF chokes (Thick line for Butterfly, Thin line for quarter wave line and Das line for
radial).
Figure 4- 28 Forward transmission vs frequency with different terminated values in
port 3 (Das line for 5 ohm, star line for 10 ohm thin line for 20 ohm and thick line for
50 ohm).
Figure 4- 29 Complete Schematic of RF choke with bias arrangement.
Figure 4- 30 Forward transmission vs frequency characteristic for the schematic of
Figure 4- 29.
Figure 4- 31 Schematic of the NE3512S02 S-parameter model before stabilization.
Figure 4- 32 Stability factor vs frequency before stabilization.
Figure 4- 33 Power gain and noise figure before stabilization.
v
Figure 4- 34 Annotation of DC simulation of stabilized FET (Electrical model) fixed
bias (IDS=20 mA and VDS=2V, VGS=-0.17V) circuit without matching network.
Figure 4- 35 Schematic of stabilized FET(S-parameter model) without matching
network.
Figure 4- 36 Stability factor vs frequency characteristic after stabilization with S-
parameter model.
Figure 4- 37 Power gain and noise figure after stabilization with S-parameter model.
Figure 4- 38 Layout component.
Figure 4- 39 Matching for noise figure at 8.5 GHz.
Figure 4- 40 Smith chart of input matching network by lumped elements.
Figure 4- 41 Input matching network where L1=1.54 nH, L2=1.87 nH, L3=1.02 nH,
L4=1.11 nH,C1=1.2 pF, C2=1.5 pF, C3=1.55 and C4=0.42 pF pF.
Figure 4- 42 Matching condition at 8.5 GHz after putting input matching network.
Figure 4- 43 Comparison between Noise figure (star line) and minimum noise (solid
line).
Figure 4- 44 Input matching network with microstrip, L1=2.1 mm, L2=2 mm, L3=2
mm, L4=3.5 mm, L5=3.57 mm, L6=1.25 mm, L7=2.38 mm and W=0.524 mm.
Figure 4- 45 Power gain and noise figure (star line) vs frequency with input matching
network.
Figure 4- 46 Matching condition at 8.5 GHz after putting input microstrip matching
network.
Figure 4- 47 Output matching network with microstrip line, L1=2 mm, L2=7 mm,
L3=2 mm, L4=2.5mm, L5=3mm, L6=2 mm, L7=4mm and W=0.524mm.Figure 4- 1
Minimum noise figure, associated gain vs. frequency characteristics [3].
Figure 4- 48 Power gain and noise figure (star line) vs frequency with input and
output network.
Figure 4- 49 LNA before matching network.
Figure 4- 50 Simulation result of LNA at 8.5 GHz matching point without matching
network.
Figure 4- 51 Smith chart for IMN design at 8.5 GHz.
Figure 4- 52 IMN at 8.5 GHz before optimize.
Figure 4- 53 IMN at 9 GHz after optimize.
Figure 4- 54 Simulation result of LNA with IMN after optimization.
Figure 4- 55 Smith chart for OMN design at 9 GHz.
Figure 4- 56 OMN at 9 GHz before optimize.
Figure 4- 57 Simulation result of LNA with optimized IMN and unutilized OMN.
Figure 4- 58 OMN at 9 GHz after optimization.
Figure 4- 59 LNA with optimize IMN and OMN at 9 GHz.
Figure 4- 60 Simulation result of LNA with IMN and OMN.
Figure 4- 61 complete layout look like LNA with IMN and OMN.
Figure 4- 62 Forward transmission (solid line) and transducer gain (dot line).
Figure 4- 63 Layout of RF choke with bias circuit; C1=10pF, C2=100 pF, C3=220
pF, C4=100nF and R1=43 Ω.
Figure 5- 1 Schematic for VIA model simulation.
Figure 5- 2 Input reflection coefficient of different via models of Figure 5- 1.
Figure 5- 3 Schematic for SMT capacitor model simulation.
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