Table Of ContentV044
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August 3,2011 15:00 RPS:Pan Stanford Publishing Book - 6.5in x 9.75in 030811-copyright
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July 28,2011 16:00 RPS:Pan Stanford Publishing Book - 6.5in x 9.75in 280711-preface
Preface
Three-dimensional (3D) integration has emerged as a critical performance
enabler for integrated circuits, at a time when the microelectornics industry
is faced with unprecedented scaling barriers, which have arisen both due to
fundamental physics and economic constraints. 3D integration provides a
mechanism for space transformation of the traditional planar implementation
of integrated circuits into three-dimensional space. It therefore provides a
pathway to extend geometrical scaling for further performance enhancement
(“More Moore”), as well as provide functional diversification (“More than
Moore”) to improve higher-level system operation. At its core, 3D integration
is simply the process of vertically stacking of circuits and forming electrical
connections between them. Despite this seemingly simple concept, however,
3D integration involves significant development of many new technologies,
from the basic processes and materials issues involved, to new approaches to
system architectures, and it is the status and progress in these new areas that
provide the focus of this book.
The advent of 3D integration is a direct result of relentless research in
academia, research laboratories, and industry over the last 10 years. Today,
3D integration exists as a diverse set of stacking and vertical interconnection
technologies that can take a multitude of forms, with the precise
implementation depending on the applications. At the time of this writing,
commercial 3D products already exist, including small form factor image
sensors that include through silicon vias (TSV), and several announcements
of future products, including 3D memory chips, have been made.
The concept of this book on 3D technology dates back to more than two years
ago. At that time, an increasing number of publications and conferences
had started to focus on 3D integration. At the end of an IEEE-sponsored
International Workshop on Next Generation Electronics in Tainan, Taiwan, in
November 2008, Pan Stanford Publishing (PSP) identified 3D integration as
an important topic for book publication. While a few reference books on this
emerging field already existsed, there was an urgent need to highlight more
recent developments in a new book and the idea of this book was formed.
Given the many varieties of 3D integration technologies and its large span in
the semiconductor supply chain, we decided to edit a book with contributions
from experts in academia, research laboratories, and industry. After careful
planning, we identified and invited chapter contribution from an impressive
line-up of highly qualified researchers. It took more than one full year for
planning, writing, and editing.
The objective of this book is to present novel ideas in pre-packaging wafer-
level 3D integration technologies. The book covers process technologies such
as wafer bonding, through silicon via (TSV), wafer thinning and handling,
infrastructures, integration schemes, design as well as providing a succinct
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vi Preface
outlook. All process technologies are carefully described and potential
applications are listed. Technical challenges are also highlighted. This book is
particularly beneficial to researchers or engineers who are already working
or are beginning to work on 3D technology.
This book would not have been possible without a team of highly qualified
and dedicated people. We are particularly grateful to Stanford Chong of PSP
for initiating this undertaking and for providing his support. Rhamie Wahap
and dedicated editorial staff at PSP worked alongside with us and provided
us with the necessary editorial support. The three co-editors were funded
for many years through the MARCO and DARPA funded Interconnect Focus
Center (IFC) as well as the DARPA funded 3D IC Program; our 3D technology
platform research, and this book, would not have been possible without this
extended research support.
C.S. Tan is immensely grateful for the unfailing love and support from his
wife, Lee Peng, without whom this book would not have been possible.
He is currently supported by a Nanyang Assistant Professorship at the
Nanyang Technological University. His research is generously supported by
a grant from the Semiconductor Research Corporation (SRC), USA, through a
subcontract from the Interconnect and Packaging Center at Georgia Institute
of Technology, a seedling fund from Defence Advanced Research Program
Agency (DARPA), USA, as well as the Defence Science and Technology Agency
(DSTA) in Singapore. K.N. Chen would like to acknowledge funding supports
from the National Science Council, Taiwan, as well as 3D IC research supports
from the National Chiao Tung University, IBM T.J. Watson Research Center,
and Massachusetts Institute of Technology. S. J. Koester is gratefully with
support from the University of Minnesota.
Last but not least, we are extremely thankful to authors who accepted our
invitation and contributed chapters to this book. We hope that the readers
will find this book useful in their pursuit of 3D technology. Please do not
hesitate to contact us if you have any comments or suggestions.
Chuan Seng Tan
[email protected]
Kuan-Neng ChUeSnA
[email protected]
Steven J. KoeTasitwearn
[email protected]
USA
May 2011
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Contents
Preface
Contents
v
vii
Chapter 1 3D Integration Technology – Introduction 1
Chuan Seng Tan, Kuan-Neng Chen and
and Overview
Steven J. Koester
Chapter 2 A Systems Perspective on 3D Integration: 27
Phil Emma and Eren Kursun
What is 3D? And What is 3D Good For?
Bioh Kim, Thorsten Matthias, Viorel Dragoi,
Chapter 3 Wafer Bonding Techniques 43
Markus Wimplinger and Paul Lindner
Paul Werbaneth
Chapter 4 TSV Etching 71
Arthur Keigler
Chapter 5 TSV Filling 91
Chapter 6 3D Technology Platform: Temporary Bonding 121
Mark Privett
and Release
Chapter 7 3D Technology Platform: Wafer Thinning, 139
Scott Sullivan
Stress Relief, and Thin Wafer Handling
Chapter 8 Advanced Die-to-Wafer 3D Integration 153
Takafumi Fukushima, Kang-Wook Lee,
Platform: Self-Assembly Technology
Tetsu Tanaka and Mitsumasa Koyanagi
Paul Enquist
Chapter 9 Advanced Direct Bond Technology 175
Chapter 10 Surface Modification Bonding at Low 205
Temperature for Three-Dimensional
Akitsu Shigetou
Hetero-Integration
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viii Contents
Chapter 11 Through Silicon Via Implementation in CMOS 231
Xavier Gagnard and Nicolas Hotellier
Image Sensor Product
Chapter 12 A 300-mm Wafer-Level Three-Dimensional 263
Integration Scheme Using Tungsten Through-
Fei Liu
Silicon Via and Hybrid Cu-Adhesive Bonding
Chapter 13 Power Delivery in 3D IC Technology with a 297
Stratum Having an Array of Monolithic
Ron Rutman and Jian Sun
DC-DC Point-of-Load (PoL) Converter Cells
Xiaoxia Wu, Yuan Xie and Vijaykirshnan
Chapter 14 Thermal-Aware 3D IC Designs 313
Narayanan
Chapter 15 3D IC Design Automation Considering 335
Hao Yu and Xiwei Huang
Dynamic Power and Thermal Integrity
Ya Lan Yang
Chapter 16 Outlook 351
Index
367
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Chapter 1
3D INTEGRATION TECHNOLOGY –
INTRODUCTION AND OVERVIEW
Chuan Seng Tan
Nanyang Technological University
Steven J. Koester
University of Minnesota
Kuan-Neng Chen
National Chiao Tung University
1.1 INTRODUCTION
The past decade has seen three-dimensional (3D) integration technology
mature rapidly from a hypothetical concept to a technology that is on the
cusp widespread commercial implementation. This rapid trend towards
acceptance of 3D integration has been both a result of key demonstrations
of the technical feasibility of the process, as well as a growing consensus that
3D integration will be necessary to continue current computational system
performance trends. 3D technology also offers an abundance of opportunities
for new applications and functionality. In this introduction, we provide an
overview of the system needs that are driving 3D integration development,
the recent advances in the underlying technology that have been key to its
recent acceptance, and new opportunities for additional functionality that
33DD I nhteagsr attihoen pfoor tVeLnSIt Siayslt etom sprovide.
Edited by Chuan Seng Tan, Kuan-Neng Chen and Steven J. Koester
Copyright © 2012 by Pan Stanford Publishing Pte. Ltd.
www.panstanford.com
