12-Bit, 210 MSPS ADC With DDR LVDS/CMOS Outputs

57 Pages·2017·2.02 MB·English

ADS5527
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SLWS196A–DECEMBER2006–REVISEDMAY2007
12-BIT, 210 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
FEATURES DESCRIPTION
• MaximumSampleRate:210MSPS ADS5527 is a high performance 12-bit, 210-MSPS
• 12-BitResolution A/D converter. It offers state-of-the art functionality
• No MissingCodes and performance using advanced techniques to
minimize board space. With high analog bandwidth
• TotalPower Dissipation 1.23W
and low jitter input clock buffer, the ADC supports
• InternalSampleandHold both high SNR and high SFDR at high input
• 70.5-dBFS SNR at70-MHzIF frequencies. It features programmable gain options
that can be used to improve SFDR performance at
• 84-dBcSFDRat70-MHzIF,0-dBgain
lowerfull-scaleanaloginput ranges.
• HighAnalog Bandwithupto800MHz
In a compact 48-pin QFN, the device offers fully
• DoubleDataRate (DDR)LVDSand Parallel
differential LVDS DDR (Double Data Rate) interface
CMOSOutputOptions while parallel CMOS outputs can also be selected.
• ProgrammableGainupto6dBforSNR/SFDR Flexible output clock position programmability is
Trade-OffatHighIF available to ease capture and trade-off setup for hold
times. At lower sampling rates, the ADC can be
• ReducedPower ModesatLowerSample
operated at scaled down power with no loss in
Rates
performance. The ADS5527 includes an internal
• SupportsInputClockAmplitudeDownto reference, while eliminating the traditional reference
400mV pins and associated external decoupling. The device
PP
• ClockDutyCycleStabilizer alsosupportsanexternalreferencemode.
• No ExternalReferenceDecouplingRequired The device is specified over the industrial
• InternalandExternalReferenceSupport temperaturerange(-40(cid:176) Cto 85(cid:176) C).
• ProgrammableOutputClockPositiontoEase
ADS5527PRODUCTFAMILY
DataCapture
210MSPS 190MSPS 170MSPS
• 3.3-VAnalogand DigitalSupply
14bit ADS5547 ADS5546 ADS5545
• 48-QFNPackage(7mm· 7mm)
12bit ADS5527 - ADS5525
APPLICATIONS
• WirelessCommunicationsInfrastructure
• SoftwareDefinedRadio
• PowerAmplifierLinearization
• 802.16d/e
• TestandMeasurementInstrumentation
• HighDefinitionVideo
• MedicalImaging
• RadarSystems
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas
Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2006–2007,TexasInstrumentsIncorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarilyincludetestingofallparameters.
ADS5527
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SLWS196A–DECEMBER2006–REVISEDMAY2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
D D
D D D N
D N V G
V G R R
A A D D
CLKP CLKOUTP
CLOCKGEN
CLKM CLKOUTM
D0_D1_P
D0_D1_M
D2_D3_P
D2_D3_M
D4_D5_P
D4_D5_M
INP Digital
12-Bit Encoder D6_D7_P
SHA
ADC and
D6_D7_M
INM Serializer
D8_D9_P
D8_D9_M
D10_D11_P
D10_D11_M
Control
VCM Reference
Interface
OVR
F K N A T E S E
RE CL SE AT SE O DF OD LVDS MODE
I S SD RE M
PACKAGE/ORDERINGINFORMATION(1)
SPECIFIED TRANSPORT
PACKAGE- PACKAGE PACKAGE ORDERING
PRODUCT TEMPERATURE MEDIA,
LEAD DESIGNATOR MARKING NUMBER
RANGE QUANTITY
TapeandReel,
ADS5527IRGZT
250
ADS5527 QFN-48(2) RGZ –40(cid:176) Cto85(cid:176) C AZ5527
TapeandReel,
ADS5527IRGZR
2500
(1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI
websiteatwww.ti.com.
(2) Forthermalpadsizeonthepackage,seethemechanicaldrawingsattheendofthisdatasheet.q =25.41(cid:176) C/W(0LFMairflow),
JA
q =16.5(cid:176) C/Wwhenusedwith2oz.coppertraceandpadsoldereddirectlytoaJEDECstandardfourlayer3inx3in(7.62cmx7.62
JC
cm)PCB.
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ABSOLUTE MAXIMUM RATINGS(1)
overoperatingfree-airtemperaturerange(unlessotherwisenoted)
VALUE UNIT
Supplyvoltagerange,AVDD –0.3Vto3.9 V
Supplyvoltagerange,DRVDD –0.3Vto3.9 V
VoltagebetweenAGNDandDRGND -0.3to0.3 V
VoltagebetweenAVDDtoDRVDD -0.3to3.3 V
VoltageappliedtoVCMpin(inexternalreferencemode) -0.3to1.8 V
Voltageappliedtoanaloginputpins,INPandINM –0.3Vtominimum(3.6,AVDD+0.3V) V
Voltageappliedtoinputclockpins,CLKPandCLKM -0.3VtoAVDD+0.3V V
T Operatingfree-airtemperaturerange –40to85 (cid:176) C
A
T Operatingjunctiontemperaturerange 125 (cid:176) C
J
T Storagetemperaturerange –65to150 (cid:176) C
stg
(1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings
onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating
conditionsisnotimplied.Exposuretoabsolutemaximumratedconditionsforextendedperiodsmayaffectdevicereliability.
RECOMMENDED OPERATING CONDITIONS
overoperatingfree-airtemperaturerange(unlessotherwisenoted)
MIN TYP MAX UNIT
SUPPLIES
Analogsupplyvoltage,AVDD 3 3.3 3.6 V
Digitalsupplyvoltage,DRVDD 3 3.3 3.6 V
ANALOGINPUTS
Differentialinputvoltagerange 2 V
PP
Inputcommon-modevoltage 1.5– 0.1 V
VoltageappliedonVCMinexternalreferencemode 1.45 1.5 1.55 V
CLOCKINPUT
Inputclocksamplerate (1) MSPS
DEFAULTSPEEDmode 50 210
MSPS
LOWSPEEDmode 1 60
Inputclockamplitudedifferential(V -V )
(CLKP) (CLKM)
Sinewave,ac-coupled 0.4 1.5 V
PP
LVPECL,ac-coupled 1.6 V
PP
LVDS,ac-coupled 0.7 V
PP
LVCMOS,single-ended,ac-coupled 3.3 V
Inputclockdutycycle(SeeFigure31) 35% 50% 65%
DIGITALOUTPUTS
C MaximumexternalloadcapacitancefromeachoutputpintoDRGND(LVDSandCMOSmodes)
L
Withoutinternaltermination(defaultafter
5 pF
reset)
With100W internaltermination (2) 10 pF
R DifferentialloadresistancebetweentheLVDSoutputpairs(LVDSmode) 100 W
L
Operatingfree-airtemperature –40 85 (cid:176) C
(1) SeethesectiononLowSamplingFrequencyOperationformoreinformation.
(2) SeethesectiononLVDSBufferInternalterminationformoreinformation.
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ELECTRICAL CHARACTERISTICS
Typicalvaluesareat25(cid:176) C,minandmaxvaluesareacrossthefulltemperaturerangeT =–40(cid:176) CtoT =85(cid:176) C,
MIN MAX
AVDD=DRVDD=3.3V,samplingrate=210MSPS,sinewaveinputclock,1.5V differentialclockamplitude,50%clock
PP
dutycycle,–1dBFSdifferentialanaloginput,internalreferencemode,0-dbgain,DDRLVDSdataoutput(unlessotherwise
noted)
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
Resolution 12 bits
ANALOGINPUT
Differentialinputvoltagerange 2 V
PP
Differentialinputcapacitance 7 pF
Analoginputbandwidth 800 MHz
Analoginputcommonmodecurrent 342 m A
(perinputpin)
REFERENCEVOLTAGES
V Internalreferencebottomvoltage Internalreferencemode 0.5 V
(REFB)
V Internalreferencetopvoltage Internalreferencemode 2.5 V
(REFT)
D V Internalreferenceerror V -V -60 – 25 60 mV
(REF) (REFT) (REFB)
V Commonmodeoutputvoltage Internalreferencemode 1.5 V
CM
VCMoutputcurrentcapability Internalreferencemode – 4 mA
DCACCURACY
NoMissingCodes Assured
DNL Differentialnon-linearity -0.8 0.5 1.0 LSB
INL Integralnon-linearity -2 1 2 LSB
Offseterror -10 5 10 mV
Offsettemperaturecoefficient 0.002 ppm/(cid:176) C
Gainerrorduetointernalreference (D V /2.0V)% -3 – 1 3 %FS
(REF)
erroralone
Gainerrorexcludinginternalreference -2 – 1 2 %FS
error(1)
Gaintemperaturecoefficient 0.01 D %/(cid:176) C
PSRR DCPowersupplyrejectionratio 0.6 mV/V
POWERSUPPLY
I Analogsupplycurrent 306 mA
(AVDD)
LVDSmode,I =3.5mA,
R =100W ,CO=5pF 66 mA
L L
I Digitalsupplycurrent
(DRVDD)
CMOSmode,F =2.5MHz,
IN 47 mA
C =5pF
L
I Totalsupplycurrent LVDSmode 372 mA
CC
Totalpowerdissipation LVDSmode 1.23 1.375 W
Standbypower InSTANDBYmodewithclockstopped 100 150 mW
Clockstoppower Withinputclockstopped 100 150 mW
(1) Gainerrorisspecifiedfromdesignandcharacterization;itisnottestedinproduction.
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ELECTRICAL CHARACTERISTICS
Typicalvaluesareat25(cid:176) C,minandmaxvaluesareacrossthefulltemperaturerangeT =–40(cid:176) CtoT =85(cid:176) C,
MIN MAX
AVDD=DRVDD=3.3V,samplingrate=210MSPS,sinewaveinputclock,1.5V differentialclockamplitude,50%clock
PP
dutycycle,–1dBFSdifferentialanaloginput,internalreferencemode,0-dbgain,DDRLVDSdataoutput(unlessotherwise
noted)
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
ACCHARACTERISTICS
F =20MHz 70.7
IN
F =70MHz 68 70.5
IN
F =100MHz 70.3
IN
F =170MHz 69.5
IN
0dBgain,2V FS(1) 69.4
PP
SNR Signaltonoiseratio F =230MHz dBFS
IN
3dBgain,1.4V FS 68
PP
0dBgain,2V FS 68.5
PP
F =300MHz
IN
3dBgain,1.4V FS 67.4
PP
0dBgain,2V FS 67.3
PP
F =400MHz
IN
3dBgain,1.4V FS 66.4
PP
RMSoutputnoise Inputstiedtocommon-mode 0.35 LSB
F =20MHz 86
IN
F =70MHz 75 84
IN
F =100MHz 78
IN
F =170MHz 79
IN
0dBgain,2V FS 75
PP
SFDR Spuriousfreedynamicrange F =230MHz dBc
IN
3dBgain,1.4V FS 78
PP
0dBgain,2V FS 74
PP
F =300MHz
IN
3dBgain,1.4V FS 76
PP
0dBgain,2V FS 68
PP
F =400MHz
IN
3dBgain,1.4V FS 70
PP
F =20MHz 70.5
IN
F =70MHz 67.5 70.2
IN
F =100MHz 69.3
IN
F =170MHz 68.0
IN
F =230MHz 0dBgain,2V FS 67.4
IN PP
SINAD Signaltonoiseanddistortionratio dBFS
3dBgain,1.4V FS 67.1
PP
0dBgain,2V FS 66.4
PP
F =300MHz
IN
3dBgain,1.4V FS 66.3
PP
0dBgain,2V FS 63.5
PP
F =400MHz
IN
3dBgain,1.4V FS 65.0
PP
F =20MHz 91
IN
F =70MHz 75 88
IN
F =100MHz 87
IN
F =170MHz 87
IN
F =230MHz 0dBgain,2V FS 86
IN PP
HD2 Secondharmonic dBc
3dBgain,1.4V FS 88
PP
0dBgain,2V FS 78
PP
F =300MHz
IN
3dBgain,1.4V FS 80
PP
0dBgain,2V FS 69
PP
F =400MHz
IN
3dBgain,1.4V FS 71
PP
(1) FS=Fullscalerange
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ELECTRICAL CHARACTERISTICS (continued)
Typicalvaluesareat25(cid:176) C,minandmaxvaluesareacrossthefulltemperaturerangeT =–40(cid:176) CtoT =85(cid:176) C,
MIN MAX
AVDD=DRVDD=3.3V,samplingrate=210MSPS,sinewaveinputclock,1.5V differentialclockamplitude,50%clock
PP
dutycycle,–1dBFSdifferentialanaloginput,internalreferencemode,0-dbgain,DDRLVDSdataoutput(unlessotherwise
noted)
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
F =20MHz 86
IN
F =70MHz 75 84
IN
F =100MHz 78
IN
F =170MHz 79
IN
0dBgain,2V FS 75
PP
HD3 Thirdharmonic F =230MHz dBc
IN
3dBgain,1.4V FS 78
PP
0dBgain,2V FS 74
PP
F =300MHz
IN
3dBgain,1.4V FS 76
PP
0dBgain,2V FS 68
PP
F =400MHz
IN
3dBgain,1.4V FS 70
PP
F =20MHz 95
IN
F =70MHz 92
IN
F =100MHz 92
IN
Worstharmonic(otherthanHD2,HD3) F =170MHz 90 dBc
IN
F =230MHz 90
IN
F =300MHz 88
IN
F =400MHz 87
IN
F =20MHz 83
IN
F =70MHz 73 82
IN
F =100MHz 76
IN
THD Totalharmonicdistortion F =170MHz 77 dBc
IN
F =230MHz 73
IN
F =300MHz 72
IN
F =400MHz 65
IN
ENOB Effectivenumberofbits F =70MHz 10.9 11.4 bits
IN
F =50.03MHz,F =46.03MHz, 91
IN1 IN2
-7dBFSeachtone
IMD Two-toneintermodulationdistortion dBFS
F =190.1MHz,F =185.02MHz,
IN1 IN2 86
-7dBFSeachtone
PSRR ACpowersupplyrejectionratio 30MHz,200mV signalon3.3-Vsupply 35 dBc
PP
Recoveryto1%(offinalvalue)for6-dBoverload Clock
Voltageoverloadrecoverytime 1
withsine-waveinputatNyquistfrequency cycles
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DIGITAL CHARACTERISTICS(1)
TheDCspecificationsrefertotheconditionwherethedigitaloutputsarenotswitching,butarepermanentlyatavalidlogic
level0or1AVDD=DRVDD=3.3V,I =3.5mA,R =100W (2)
O L
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
DIGITALINPUTS
High-levelinputvoltage 2.4 V
Low-levelinputvoltage 0.8 V
High-levelinputcurrent 33 m A
Low-levelinputcurrent –33 m A
Inputcapacitance 4 pF
DIGITALOUTPUTS–CMOSMODE
High-leveloutputvoltage 3.3 V
Low-leveloutputvoltage 0 V
Outputcapacitance Outputcapacitanceinsidethedevice,fromeachoutputto 2 pF
ground
DIGITALOUTPUTS–LVDSMODE
High-leveloutputvoltage 1375 mV
Low-leveloutputvoltage 1025 mV
Outputdifferentialvoltage,|V | 225 350 425 mV
OD
V Outputoffsetvoltage,single-ended Common-modevoltageofOUTPandOUTM 1200 mV
OS
Outputcapacitanceinsidethedevice,fromeitheroutputto
Outputcapacitance 2 pF
ground
(1) AllLVDSandCMOSspecificationsarecharacterized,butnottestedatproduction.
(2) I referstotheLVDSbuffercurrentsetting,R isthedifferentialloadresistancebetweentheLVDSoutputpair.
O L
TIMING CHARACTERISTICS – LVDS AND CMOS MODES(1)
Typicalvaluesareat25(cid:176) C,minandmaxvaluesareacrossthefulltemperaturerangeT =–40(cid:176) CtoT =85(cid:176) C,AVDD=
MIN MAX
DRVDD=3.3V,samplingfrequency=210MSPS,sinewaveinputclock,1.5V clockamplitude,C =5pF(2),I =3.5mA,
PP L O
R =100W (3),nointernaltermination,unlessotherwisenoted.
L
Fortimingsatlowersamplingfrequencies,seetheOutputTimingsectionintheAPPLICATIONINFORMATIONofthisdata
sheet.
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
t Aperturedelay 1.2 ns
a
t Aperturejitter 150 fsrms
j
Timetovaliddataaftercomingoutof
100
STANDBYmode
Wake-uptime m s
Timetovaliddataafterstoppingand
100
restartingtheinputclock
clock
Latency 14
cycles
DDRLVDSMODE(4)
t Datasetuptime(5) Datavalid (6)tozero-crossofCLKOUTP 1.0 1.5 ns
su
Zero-crossofCLKOUTPtodatabecoming
t Dataholdtime(5) 0.35 0.8 ns
h invalid(6)
(1) Timingparametersarespecifiedbydesignandcharacterizationandnottestedinproduction.
(2) C istheeffectiveexternalsingle-endedloadcapacitancebetweeneachoutputpinandground.
L
(3) I referstotheLVDSbuffercurrentsetting;R isthedifferentialloadresistancebetweentheLVDSoutputpair.
O L
(4) Measurementsaredonewithatransmissionlineof100W characteristicimpedancebetweenthedeviceandtheload.
(5) Setupandholdtimespecificationstakeintoaccounttheeffectofjitterontheoutputdataandclock.Thesespecificationsalsoassume
thatthedataandclockpathsareperfectlymatchedwithinthereceiver.Anymismatchinthesepathswithinthereceiverwouldappear
asreducedtimingmargin.
(6) Datavalidreferstologichighof+50mVandlogiclowof–50mV.
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TIMING CHARACTERISTICS – LVDS AND CMOS MODES (continued)
Fortimingsatlowersamplingfrequencies,seetheOutputTimingsectionintheAPPLICATIONINFORMATIONofthisdata
sheet.
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
Inputclockrisingedgezero-crossto
t Clockpropagationdelay(7) 3.7 4.4 5.1 ns
PDI outputclockrisingedgezero-cross
Dutycycleofdifferentialclock,
LVDSbitclockdutycycle (CLKOUTP-CLKOUTM) 45% 50% 55%
80£ Fs£ 210MSPS
Risetimemeasuredfrom–50mVto50
t , Datarisetime, mV
r 50 100 200 ps
t Datafalltime Falltimemeasuredfrom50mVto–50mV
f
1£ Fs£ 210MSPS
Risetimemeasuredfrom–50mVto50
t , Outputclockrisetime, mV
CLKRISE 50 100 200 ps
t Outputclockfalltime Falltimemeasuredfrom50mVto–50mV
CLKFALL
1£ Fs£ 210MSPS
Outputclockjitter Cycle-to-cyclejitter 120 pspp
t Outputenable(OE)tovaliddata TimetovaliddataafterOEbecomes 1 m s
OE delay active
PARALLELCMOSMODE
Datavalid(8)to50%ofCLKOUTrising ns
t Datasetuptime (5) 1.8 2.6
su edge
50%ofCLKOUTrisingedgetodata
t Dataholdtime (9) 0.4 0.8 ns
h becominginvalid(10)
Inputclockrisingedgezero-crossto50%
t Clockpropagationdelay(11) 2.6 3.4 4.2 ns
PDI ofCLKOUTrisingedge
Dutycycleofoutputclock(CLKOUT)
Outputclockdutycycle 80£ Fs£ 210MSPS 45%
Risetimemeasuredfrom20%to80%of
DRVDD
t , Datarisetime,
r Falltimemeasuredfrom80%to20%of 0.8 1.5 2.0 ns
t Datafalltime
f DRVDD
1£ Fs£ 210MSPS
Risetimemeasuredfrom20%to80%of
DRVDD
t , Outputclockrisetime,
CLKRISE Falltimemeasuredfrom80%to20%of 0.4 0.8 1.2 ns
t Outputclockfalltime
CLKFALL DRVDD
1£ Fs£ 210MSPS
Outputenable(OE)tovaliddata TimetovaliddataafterOEbecomes
t 50 ns
OE delay active
(7) Tousetheinputclockasthedatacaptureclock,itisnecessarytodelaytheinputclockbyadelay(t )togetthedesiredsetupandhold
D
times.Useeitheroftheseequationstocalculatet :
D
Desiredsetuptime=t -(t -t )
D PDI su
Desiredholdtime=(t +t )-t
PDI h D
(8) Datavalidreferstologichighof2Vandlogiclowof0.8V
(9) Setupandholdtimespecificationstakeintoaccounttheeffectofjitterontheoutputdataandclock.Thesespecificationsalsoassume
thatthedataandclockpathsareperfectlymatchedwithinthereceiver.Anymismatchinthesepathswithinthereceiverwouldappear
asreducedtimingmargin.
(10) Datavalidreferstologichighof2Vandlogiclowof0.8V
(11) Tousetheinputclockasthedatacaptureclock,itisnecessarytodelaytheinputclockbyadelay(t )togetthedesiredsetupandhold
D
times.Useeitheroftheseequationstocalculatet :
D
Desiredsetuptime=t -(t -t )
D PDI su
Desiredholdtime=(t +t )-t
PDI h D
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N+2 N+3 N+4 N+15 N+16 N+17
Sample N+1 N+14
N
Input
Signal
t
a
CLKP
Input
Clock
CLKM
CLKOUTM
CLKOUTP
t
su
t
14 Clock Cycles th PDI
DDR
LVDS
Output Data
E O E O E O E O E O E O E O E O E O E O
DXP, DXM
E–Even Bits D0,D2,D4,D6,D8,D10 N–14 N–13 N–12 N–11 N–10 N–1 N N+1 N+2
O–Odd Bits D1,D3,D5,D7,D9,D11
t
PDI
CLKOUT
t
su
Parallel
CMOS 14 Clock Cycles th
Output Data
N–14 N–13 N–12 N–11 N–10 N–1 N N+1 N+2
D0–D11
Figure1. Latency
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CLKM
Input
Clock
CLKP
t
PDI
CLKOUTP
Output
Clock
CLKOUTM
t t
h su
t t
su h
Output Dn_Dn+1_P, (NoteA) (NoteB)
Dn Dn+1
Data Pair Dn_Dn+1_M
A. Dn–BitsD0,D2,D4,D6,D8,andD10
B. Dn+1–BitsD1,D3,D5,D7,D9,andD11
Figure2.LVDSModeTiming
CLKM
Input
Clock
CLKP
t
PDI
Output
CLKOUT
Clock
t
h
t
su
Output (NoteA)
Dn Dn
Data
A. Dn–BitsD0–D11
Figure3. CMOSModeTiming
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