Wideband Amplifier Design for STO Technology

114 Pages·2011·2.09 MB·English

by  Tingsu Chen

Wideband Amplifier Design for
STO Technology

Master of Science Thesis
In System-on-Chip Design

by

Chen Tingsu
[email protected]

Stockholm, August, 2011

Supervisor: Prof. Ana Rusu and Dr. Saúl Rodríguez Dueñas
Examiner: Prof. Ana Rusu

August 30, 2011
Master Thesis TRITA-ICT-EX-2011:204
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ACKNOWLEDGEMENTS

First and foremost, I would like to take the opportunity to extend my greatest
gratitude to my main supervisor Professor Ana Rusu for welcoming me to the Radio
and Mixed-Signal group at KTH, providing me good suggestions for both research
and life, guiding me for research topic definition and the overall research plan,
supporting me during these months and reviewing manuscripts. Professor Ana Rusu is
an innate scientific leader, an endless source of inspiration and excellent example to
follow.

I would like to appreciate my co-supervisor Dr. Saúl Alejandro Rodríguez Dueñas for
his patient guidance, frequent troubleshooting and valuable discussion during the
whole design. He shows talent, creativity, responsibility and strict discipline at all
times. He is a professional model to follow.

I also want to thank Professor Eduard Alarcón Cot and Julian Marcos Garcia for
providing references, good suggestions and valuable discussion during my thesis
work.

My thanks are also to Bengt Molin for sharing his great knowledge and experience in
analog and RF electronics. His precise attitude on teaching inspires me.

I would like to thank Professor Johan Åkerman and Anders Eklund for providing me
valuable references of novel STO technology.

I also sincerely want to thank Xu Dongdong (bachelor thesis supervisor). He is my
respectable teacher and friend.

I would want to acknowledge all the friends in the Radio and Mixed-Signal group,
where is full of passion and intelligence: Sha Tao, Vasileios Manolopoulos, Raul Onet,
Milad Razzaghpour and Rocco Grimaldi.

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I want to thank all my friends in the System-On-Chip Design program.

Last, but not the least, I wish to express my deep appreciation to my parents in China
for their infinite love in my life.
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ABSTRACT

Spin Torque Oscillator (STO) is a promising technology for microwave and radar
applications due to its large tunability, miniature size, high operation frequency, high
integration level, etc. However, the technology comes also with issues and challenges,
such as low output power and spectrum impurity. For instance, in order to apply the
STO technology into communication systems, an amplifier is required to compensate
the STO’s low output power.
This thesis presents an amplifier for promising Magnetic Tunnel Junction
(MTJ) STO devices. The motional resistance of different MTJ STO devices varies
from several Ohms to hundreds Ohms, which makes the design challenging. This
thesis focuses first on extracting the amplifier requirements using the state-of-the-art
MTJ STO devices. The operation frequency of MTJ STO is in the range of 4-8GHz
with a -40～-60 dBm output power. Therefore, a wideband amplifier with 45-65 dB
gain is required. Then based on the amplifier requirements, an amplifier topology is
proposed, which is composed of two types of input balun-LNA stages depending on
the motional resistance of the STO, a broadband limiting amplifier and an output
buffer. CG-CS architecture is suitable for the input balun-LNA in the small motional
resistance case and cascoded-CS architecture is suitable for the large motional
resistance case. The limiting amplifier and the output buffer are the common circuits
shared by two cases via switches.
The wideband amplifier for STO is implemented using a 65nm CMOS process
with 1.2V supply and it exhibits 52.36 dB gain with 1.34-11.8 GHz bandwidth in
small motional resistance case and 59.29 dB gain with 1.171-8.178 GHz bandwidth in
large motional resistance case. The simulation results show that the amplifier has very
low power consumption and meets the linearity and noise performance requirements.

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ABBREVIATION TABLE

Abbrev. Full names
AC Alternating Current
CCO Current-Controlled Oscillator
CG Common Gate
CMOS Complementary Metal-Oxide Semiconductor
CS Common Source
dB Decibel
dBm Power ratio in decibels of the measured power referenced to
one milliwatt
DC Direct Current
ESD Electrical Static Discharge
Ft Transit Frequency
gm Transconductance
GMR Giant Magnetic Resistance
IIP3 Third-Order Input Intercept Point
IP3 Third-order Intercept Point
LA Limiting Amplifier
LNA Low Noise Amplifier
LSB Load Stability Circle
MR Magneto-Resistance
MTJ Magnetic Tunnel Junctions
NF Noise Figure
OIP3 Output Third-Order Intercept Point
PAC Periodic AC
PCB Printed Circuit Board
PLL Phase-Locked Loop
PSS Periodic Steady-Stage
Rds Drain to Source Resistance
Recn Resistor for Thermal Noise Enhancement
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RAM Random Access Memory
RF Radio Frequency
SRF Self-Resonant Frequency
SSB Source Stability Circle
STO Spin Torque Oscillator
TIA Transimpedance Amplifier
TMR Tunnel Magnetic Resistance
VCO Voltage-Controlled Oscillator
Vdd Power Supply Voltage
Vpp Peak-to-peak voltage
VSWR Voltage Standing Wave Ratio
VTH Threshold voltage of Transistor

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CONTENTS

ACKNOWLEDGEMENTS ......................................................................................... i
ABBREVIATION TABLE ......................................................................................... iv
CONTENTS................................................................................................................. vi
LIST OF FIGURES ................................................................................................. viii
LIST OF TABLES ....................................................................................................... xi
Chapter 1. Introduction ............................................................................................... 1
1.1 Motivation ......................................................................................................... 1
1.2 Objectives ......................................................................................................... 2
1.3 Thesis Organization .......................................................................................... 3
Chapter 2. Spin Torque Oscillator .............................................................................. 5
2.1 Background ....................................................................................................... 5
2.1.1 Spin momentum transfer torque .............................................................. 5
2.1.2 Magneto-resistance ................................................................................. 6
2.2 Characterization of Spin Torque Oscillator ...................................................... 7
2.2.1. Features and drawbacks ......................................................................... 7
2.2.2. Classification.......................................................................................... 8
2.3 State-of-the-art MTJ STO ................................................................................. 9
2.4 Summary ......................................................................................................... 13
Chapter 3. Amplifier Requirements and Topology ................................................. 14
3.1 Amplifier Requirements.................................................................................. 14
3.2 Cases under investigations .............................................................................. 17
3.2.1. Small motional resistance case ............................................................ 17
3.2.2. Large motional resistance case ............................................................ 19
3.3 Amplifier Topology ........................................................................................ 20
3.4 Summary ......................................................................................................... 23
Chapter 4. Bias-tee and Current Source/Sink ......................................................... 24
4.1 Bias-tee ........................................................................................................... 24
4.1.1 Bias-tee Operation ................................................................................ 24
4.1.2 Transfer function ................................................................................... 25
4.2 Biasing circuit and Current Source/Sink design ............................................. 27
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4.2.1. Small motional resistance case ............................................................ 27
4.2.2. Large motional resistance case ............................................................ 33
4.3 Summary ......................................................................................................... 34
Chapter 5. Input Stage of Amplifier ......................................................................... 35
5.1 Input stage in small motional resistance case ................................................. 35
5.2 Input stage in large motional resistance case .................................................. 46
5.3 Switch ............................................................................................................. 54
5.4 Summary ......................................................................................................... 55
Chapter 6. Limiting amplifier ................................................................................... 56
6.1 Limiting amplifier ........................................................................................... 56
6.2 Case studies ..................................................................................................... 57
6.2.1 Cascaded LA using CS stages ............................................................... 57
6.2.2 Cascaded LA using CS stages with negative Miller capacitors
compensation ................................................................................................. 58
6.2.3 Cascaded LA using cascoded CS stages ............................................... 60
6.2.4 Cascaded LA using current mirror ........................................................ 61
6.2.5 Topology discussion .............................................................................. 62
6.3 Limiting amplifier Design for STO amplifier ................................................. 63
6.4 Summary ......................................................................................................... 73
Chapter 7. Output buffer .......................................................................................... 74
7.1 Case studies ..................................................................................................... 74
7.2 Output buffer design ....................................................................................... 75
7.3 Summary ......................................................................................................... 80
Chapter 8. Wideband amplifier Design ................................................................... 81
8.1 Small motional resistance case (50 Ohms system) ......................................... 81
8.2 Large motional resistance case (High-Z system) ............................................ 88
8.3 Summary ......................................................................................................... 94
Chapter 9. Conclusion and Future Work ................................................................ 95
9.1 Conclusion ...................................................................................................... 95
9.2 Future Work .................................................................................................... 96
Reference .................................................................................................................... 97
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LIST OF FIGURES

Figure 2.1 STO structure and magneto-resistance effect ........................................ 5
Figure 2.2 Spin momentum transfer torque ............................................................ 6
Figure 2.3 Two types of MTJ STO ......................................................................... 9
Figure 2.4 Timetrace of MTJ STO after a 62 dB amplifier .................................. 11
Figure 2.5 PSD over 1us of the MTJ timetrace after a 62 dB amplifier ............... 12
Figure 3.1 Block Diagram of this project ............................................................. 15
Figure 3.2 Modified impedance matching ............................................................ 19
Figure 3.3 Broadband amplifier based on voltage-controlled current source with
resistive feedback .......................................................................................... 20
Figure 3.4 Low noise amplifier with matching networks at input and output ...... 20
Figure 3.5 Basic common-gate stage with capacitive coupling at input ............... 21
Figure 3.6 Amplifier topology .............................................................................. 22
Figure 4.1 Bias-tee architecture (a).RC architecture (b).LC architecture ............. 24
Figure 4.2 Bias-tee LC architecture ...................................................................... 25
Figure 4.3 Bias-tee RC architecture ...................................................................... 26
Figure 4.4 (a).Model of real inductor L (b).Model of real capacitor C ................ 27
Figure 4.5 Dual current source/sink and biasing topology ................................... 29
Figure 4.6 Biasing and current source/sink in small motional resistance case ..... 30
Figure 4.7 Impedance of biasing and current source/sink .................................... 30
Figure 4.8 Impedance Z11 of biasing and current source/sink ............................. 31
Figure 4.9 S-parameter analysis of biasing and current sink ................................ 32
Figure 4.10 S-parameter analysis of biasing and current source .......................... 33
Figure 5.1 The lumped circuit model of bond wire .............................................. 35
Figure 5.2 Approximate package model ............................................................... 36
Figure 5.3 CG-CS balun-LNA – input stage ......................................................... 37
Figure 5.4 Input impedance of the balun-LNA ..................................................... 40
Figure 5.5 S11 of the balun-LNA ......................................................................... 40
Figure 5.6 Biasing circuit for CG-CS balun-LNA – input stage........................... 41
Figure 5.7 Gain of balun-LNA with same gain at CG and CS branches .............. 42
Figure 5.8 Noise performance of LNA ................................................................. 43
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Figure 5.9 Source Stability Circle of the LNA ..................................................... 45
Figure 5.10 Transient analysis of input stage........................................................ 45
Figure 5.11 IIP3 of CG-CS LNA .......................................................................... 46
Figure 5.12 Cascoded CS input stage ................................................................... 47
Figure 5.13 Biasing circuit for Cascoded CS balun-LNA .................................... 48
Figure 5.14 AC responses of cascoded CS stage .................................................. 50
Figure 5.15 Input impedance with bond wire effect at 5 GHz .............................. 50
Figure 5.16 Input impedance of the cascoded CS stage ....................................... 50
Figure 5.17 Noise performances of cascoded CS stages ...................................... 51
Figure 5.18 Transient analysis of cascoded CS stages .......................................... 52
Figure 5.19 IIP3 of cascoded CS LNA ................................................................. 52
Figure 5.20 gds vs. Vds and Rds vs. Vds characteristics of switch transistor ...... 55
Figure 6.1 CS stage of Limiting amplifier ............................................................ 57
Figure 6.2 Simulation result of CS stage .............................................................. 58
Figure 6.3 CS stage with negative Miller capacitors compensation ..................... 59
Figure 6.4 Simulation result of CS stage with negative Miller capacitors
compensation ................................................................................................ 59
Figure 6.5 Cascoded CS stage .............................................................................. 60
Figure 6.6 Simulation result of cascoded CS stage of Limiting amplifier............ 61
Figure 6.7 Current mirror stage ............................................................................ 61
Figure 6.8 Simulation result of current mirror stage............................................. 62
Figure 6.9 Synthesizing wideband frequency responses ...................................... 64
Figure 6.10 LA cell ............................................................................................... 65
Figure 6.11 Model of inductive peaking compensation ........................................ 65
Figure 6.12 Simplified model of LA cell .............................................................. 66
Figure 6.13 AC response of CS stage ................................................................... 68
Figure 6.14 Simulation results of 6-stage LA ....................................................... 69
Figure 6.15 Noise Figure of 6 cascoded CS stages of LA .................................... 70
Figure 6.16 Transient analysis of LA .................................................................... 71
Figure 7.1 Output buffer ....................................................................................... 75
Figure 7.2 Bond wire at the output ....................................................................... 76
Figure 7.3 Output impedance of output buffer (3 GHz to 10 GHz) ..................... 77
Figure 7.4 Output reflection coefficient S22 of output buffer .............................. 78
Figure 7.5 Gain loss of output buffer .................................................................... 78
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