VLSI Placement and Global Routing Using Simulated Annealing

297 Pages·1988·13.63 MB·English

by  Carl Sechen (auth.)

VLSI PLACEMENT AND GLOBAL ROUTING
USING SIMULATED ANNEALING
THE KLUWER INTERNATIONAL SERIES
IN ENGINEERING AND COMPUTER SCIENCE
VLSI, COMPUTER ARCHITECTURE AND
DIGITAL SIGNAL PROCESSING
Consulting Editor
Jonathan Allen
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Computer-Aided Design and VLSI Device Development, K. M. Cham, S. -Yo Oh, D. Chin and
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Introduction to VLSI Silicon Devices:Physics, Technology and Characterization, B. EI-Kareh
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VLSI PLACEMENT
AND GLOBAL ROUTING USING
SIMULATED ANNEALING
by
Carl See hen
Yale University
~.
"
Kluwer Academic Publishers
Boston/Dordrecht/London
Distributors for North America:
Kluwer Academic Publishers
101 Philip Drive
Assinippi Park
Norwell, Massachusetts 02061, USA
DIstributors for the UK and Ireland:
Kluwer Academic Publishers
Falcon House, Queen Square
Lancaster LAI IRN, UNITED KINGDOM
Distributors for all other countries:
Kluwer Academic Publishers Group
Distribution Centre
Post Office Box 322
3300 AH Dordrecht, THE NETHERLANDS
LIbrary of Congress Cataloglng·ln.Publicatlon Data
Sechen, Carl, 1956-
VLSI placement and global routing using simulated annealing/by
Carl Sechen.
p. cm.-(The Kluwer international series in engineering and
computer science; 54)
Bibliography: p.
Includes index.
ISBN·13: 978·1·4612·8957·9 e·ISBN·13: 978·1·4613·1697·8
001: 10.1007/978·1·4613·1697·8
I. Integrated circuits-Very large scale integration-Design and
construction. I. Title. II. Series; Kluwer international series
in engineering and computer science; SECS 54
TK7874.S38 1988 88-12889
621.395-dc19 CIP
Copyright © 1988 by Kluwer Academic Publishers, Boston. Second Printing 1997.
Softcover reprint of the hardcover 1st edition 1988
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or
transmitted in any form or by any means, mechanical, photocopying, recording, or otherwise, without
the prior written permission of the publisher, Kluwer Academic Publishers, 101 Philip Drive, Assinippi
Park, Norwell, Massachusetts 02061.
Table of Contents
Preface ................................ " ............................................................ xiii
List of Figures ..............•••... '" .............................................................. xv
List of Tables ..•••....................•............................................................ xxiii
Chapter 1 Introduction ............................ , ............................................... 1
1.1 Placement and Global Routing of Integrated Circuits ............................ 1
1.2.1 The gate array placement and global routing problem ................ 5
1.2.2 The standard cell placement and global routing problem ............. 10
1.2.3 The macro/custom cell placement and global routing problem ...... 11
1.3 Previous Approaches to Placement and Global Routing ........................ 13
1.3.1 Previous placement methods ............................................ 13
1.3.2 Previous global routing methods ........................................ 18
1.4 A New Approach to Cell-Based Placement and Global Routing ............... 23
Chapter 2 The Simulated Annealing Algorithm .................................................. 31
21 Introduction ........................................................................... 31
22 The Basic Simulated Annealing Algorithm. ....................................... 35
2.3 Theoretical Investigations of the Simulated Annealing Algorithm. ............. 37
2.4 Overview of Work on General Annealing Schedules ............................ 41
vi VLSI Place~nt and Global Routing Using Simulated Annealing
2.4.1 The initial temperature .................................................... 42
2.4.2 The temperature decrement .............................................. 42
2.4.3 The equilibrium condition ................................................ 43
2.4.4 The stopping, or convergence, criterion ............................... 44
2.5 Implementations of Simulated Annealing for Placement and Global
Routing ................................................................................ 44
2.6 The Function fO ...................................................................... 45
2.7 Fast Evaluation of the Exponential Function. ..................................... 47
Chapter 3 Placement and Global Routing of Standard Cell Integrated Circuits .............. 51
3.1 Introduction ........................................................................... 51
3.2 The General TimberWolfSC Methodology ....................................... 53
3.2.1 Finding the optimal target row lengths ................................. 54
3.2.2 Critical-net weighting ..................................................... 58
3.3 The Algorithm for Stage lofTimberWolfSC .................................... 58
3.3.1 The cost function .......................................................... 58
3.3.1.1 The first term in the cost function ............................ 58
3.3.1.2 The second term in the cost function ........................ 58
3.3.1.3 The third term in the cost function ........................... 62
3.3.2 An alternative objective function ........................................ 63
3.3.3 The generation of new states function .................................. 70
3.3.4 The inner loop criterion .................................................. 72
3.3.5 The range limiter .......................................................... 73
3.3.6 The control of T ........................................................... 75
3.3.7 The effects of net weighting ............................................. 77
3.4 The Algorithms for Stage 2 ofTimberWolfSC ................................... 78
Table ofC ontents vii
3.4.1 hnplementation of the stage 2 simulated annealing functions ........ 80
3.4.2 The first phase of the global router ..................................... 80
3.4.3 The second phase of the global router .................................. 84
3.5 The Algorithm for Stage 3 of TimberWolfSC .................................... 85
3.6 TimberWolfSC Results .............................................................. 87
3.6.1 Comparisons taken at the end of stage 1 ............................... 87
3.6.2 The effectiveness of the global router .................................. 88
3.6.3 The effectiveness of stage 3 of TimberWolfSC ....................... 89
3.6.4 TimberWolfSC comparisons including stage 3 ....................... 89
Chapter 4 Macro/Custom Cell Chip-Planning, Placement, and Global Routing ............ 93
4.1 Introduction ........................................................................... 93
4.2 The General TimberWolfMC Methodology. ...................................... 95
4.2.1 Algorithms for handling rectilinear cells ............................... 95
4.2.1.1 The bustO algorithm ........................................... 95
4.2.1.2 The unbustO algorithm ........................................ 99
4.2.2 Generating the initial placement configuration ........................ l09
4.2.3 Custom-cell pin placement. ............................................. 110
4.2.3.1 Introduction to the TimberWolfMC pin site
methodology .................................................. 110
4.3 The Algorithm for Stage 1 of TimberWolfMC .................................. 113
4.3.1 The cost function ......................................................... 113
4.3.1.1 The first term in the cost function ........................... I13
4.3.1.2 The second term in the cost function ....................... 114
4.3.1.3 The third term in the costfunction .......................... 121
4.3.2 The generateO function .................................................. 122
viii VLSI Placement and Global Routing Using Simulated AMealing
4.3.2.1 Introduction ................................................... 122
4.3.2.2 TheRangeLimiter ............................................ 125
4.3.2.3 Single-cell displacement-point selection ................... 128
4.3.3 Additional stage 1 simulated annealing algoritlunic details .......... 131
4.4 The Algoritluns for Stage 2 of TimberWolfMC ................................. 134
4.4.1 Channel generation ...................................................... 135
4.4.2 Global routing ............................................................ 135
4.4.3 Placement refmernent .................................................... 136
4.5 TimberWolfMC Results ............................................................ 138
4.6 Conclusion ........................................................................... 138
Chapter 5 Average Interconnection Length Estimation ........................................ 141
5.1 Introduction .......................................................................... 141
5.2 The Placement Model. .............................................................. 142
5.3 Previous Approaches ............................................................... 144
5.4 Average Interconnection Length for Random Placements under the
Assumption of Two-Pin Nets ..................................................... 146
5.4.1 Practical considerations ................................................... 147
5.5 Average Interconnection Length for Random Placements Having Nets
of Arbitrary Pin Counts ............................................................ 147
5.5.1 Results ...................................................................... 160
5.6 A Model for Optimized Placement ................................................ 163
5.6.1 The average number of other cells connected to a cell ............... 163
5.6.1.1 Thenewmethod .............................................. I64
5.6.1.2 Practical considerations ...................................... 166
5.6.1.3 Results ......................................................... I66
Table o/Contents ix
5.6.2 A notion of optimized placement ....................................... 167
5.6.3 The enclosing Cm X C, rectangles .•............•....•..........••..... 177
5.7 Results ................................................................................ 178
Chapter 6 Interconnect- Area Estimation for Macro Cell Placements ......................... 181
6.1 Introduction .......................................................................... 181
6.2 IntercOIUlect-Area Estimation Based on Average Net Traffic .................. 184
6.3 Baseline Channel Width Modulation Based on Charmel Position ........•.... 186
6.4 Associating the Estimated Interconnect Area with the Cell Edges ......•...... 190
6.5 Interconnect-Area Estimation as a Function of Relative Pin Density. ......... 191
6.6 The Implementation of the Dynamic Interconnect-Area Estimator ............ 191
6.7 Results ................................................................................ 192
Chapter 7 An Edge-Based Channel Definition Algorithm for Rectilinear Cells. ............ 199
7.1 Introduction .......................................................................... 199
7.2 The Basic Channel Defmition Algorithm ......................................... 204
7.2.1 Identifying critical cell-edge pairs ......................................2 05
7.2.2 Characterization of fixed cell edges ....................................2 06
7.2.3 An algorithm for finding critical regions ..............................2 07
7.3 The Generation of the Charmel Graph ............................................2 10
7.4 The Generation of the Channel Routing Order ..................................2 16
Chapter 8 A Graph-Based Global Router Algorithm ......................................... 229
8.1 Introduction .......................................................................... 229
8.2 Basic Graph Algorithms Used by the Global Router ........................... 231
8.2.1 Prim's algorithm for the minimum sparming tree problem. ......... 232
8.2.2 Dijkstra's algorithm forthe shortest path problem ...................2 33
x VLSI Placeml!nt and Global Routing Using Simulated Annealing
8.2.3 Lawler's algorithm for finding the M-shortest paths ................ 233
8.3 The Algorithm for Generating M-Shortest Routes for a Net. .................. 235
8.4 The Second Phase of the Global Router Algorithm ............................. 242
8.5 Results ................................................................................ 243
Chapter 9 Conclusion .............................................................................. 247
9.1 Surnrnary ............................................................................. 247
9.2 Future Work ......................................................................... 250
9.2.1 Simulated anncaling ..................................................... 250
9.2.2 Row-based cell placement .............................................. 250
9.2.3 Row-based global routing .............................................. 251
9.2.4 Macro/custom cell placement ........................................... 252
9.2.5 Interconnection Icngth estimation ...................................... 252
9.2.6 Channel defmition ....................................................... 252
9.2.7 Graph-based global routing ............................................. 252
Appendix Island-Style Gate Array Placement .................................................. 255
A.l Introduction .......................................................................... 255
A.2 The Implementation of the Simulated Annealing Functions .................... 257
A.2.1 The generation of new states ........................................... 257
A.2.2 The cost function ......................................................... 260
A.2.2.1 The first cost function ........................................ 260
A.2.2.2 The second cost function .................................... 261
A.2.3 The inner loop criterion ................................................. 262
A.2.4 The control of T .......................................................... 262
A.2.5 The stopping criterion ................................................... 265