Tree-based Heterogeneous FPGA Architectures: Application Specific Exploration and Optimization

197 Pages·2012·8.86 MB·English

by  Umer Farooq, Zied Marrakchi, Habib Mehrez (auth.)

Tree-Based Heterogeneous
FPGA Architectures
Umer Farooq Zied Marrakchi
•
Habib Mehrez
Tree-Based Heterogeneous
FPGA Architectures
Application Specific Exploration
and Optimization
123
UmerFarooq Habib Mehrez
COMSATSInstituteof Information Paris VI
Technology Laboratoire LIP6
Kamboh House Université Pierre etMarieCurie
SyedChiraghShahTown 4,Place Jussieu
Kasur 55050 75252Paris
Pakistan France
ZiedMarrakchi
FLEXRASTechnologies
BoulevardAnatole
Tour PleyelOuest 153
93521Saint Denis
France
ISBN 978-1-4614-3593-8 ISBN 978-1-4614-3594-5 (eBook)
DOI 10.1007/978-1-4614-3594-5
SpringerNewYorkHeidelbergDordrechtLondon
LibraryofCongressControlNumber:2012937466
(cid:2)SpringerScience+BusinessMediaNewYork2012
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Preface
The generalized and programmable nature of Field Programmable Gate Arrays
(FPGAs) has made them a popular choice for the implementation of digital cir-
cuits. However, the programmability of FPGAs makes them larger, slower, and
more power consuming than their counterpart ASICs; hence making them
unsuitable for applications requiring high density, performance, and low power
consumption. The main theme of this work is to improve the area of FPGAs. For
thispurpose,adetailedexplorationandoptimizationoftwoFPGAarchitecturesis
performed: one is the well-known mesh-based FPGA architecture while the other
is tree-based architecture that remains relatively unexplored despite its better
performanceandroutingpredictability.Further,adetailedcomparisonbetweenthe
two architectures is presented to highlight their respective advantages and
disadvantages.
The exploration and optimization of two architectures start with the introduc-
tion of heterogeneous hard-blocks in both architectures. In this work, first we
present a new environment for exploration of tree-based heterogeneous FPGA
architecture.Thisenvironmentisflexibleinnatureandallowstoexploredifferent
architecture techniques with varying types of hard-blocks. Further, in this work,
we present an exploration environment for mesh-based heterogeneous FPGA
architecture.Thetwoenvironmentsareusedtoexploreanumberoftechniquesfor
both architectures. These techniques are later evaluated using different heteroge-
neous benchmarks that are placed and routed on the two architectures using a
specifically developed software flow. A detailed comparison between different
techniquesofthetwoarchitecturesisperformedandresultsshowthatonaverage,
tree-based architecture gives better overall results than mesh-based architecture.
Generalized mesh and tree-based FPGA architectures are further improved by
turning them into application-specific FPGAs. An application-specific inflexible
FPGA (ASIF) is a modified FPGA with reduced flexibility and improved density.
This work initially presents a new tree-based homogeneous ASIF and when
compared to an equivalent tree-based FPGA, it gives 64% area gain. Further, the
comparisonbetween equivalent meshandtree-based ASIFsshowsthattree-based
ASIF gives 12% better area results than mesh-based ASIF. We also extend the
vii
viii Preface
ASIFtotheheterogeneousdomainandexperimentalresultsshowthat,onaverage,
tree-basedheterogeneousASIFgives70%areagainwhencomparedtoequivalent
tree-based heterogeneous FPGA. Further, the comparison between heterogeneous
mesh and tree-based ASIFs reveals that tree-based ASIF gives either equal or
better results than mesh-based ASIF.
Acknowledgments
WewouldliketotakethisopportunitytoexpressoursincerethankstotheDirector
of System on Chip Lab, Professor Alix Munier KORDON, for her efforts which
provided a wonderful work environment at SoC-LIP6.
We are extremely thankful to Mr. Daniel CHILLET, Associate Professor at
IRISALannion,Mr.LaurentFESQUET,AssociateProfessoratTIMA,Grenoble,
Professor Francois ANCEAU, Full Professor at LIP6/University Pierre & Marie
Curie, Professor Jean-Luc Danger, Full Professor at ENST/Telecom ParisTech,
andProfessorBertrandGRANADO,FullProfessoratENSEA,CergyPontoisefor
reviewing this work. We are particularly thankful to Professor Christian Masson
who perceived the importance of this work at its preliminary stage and gave very
useful insights for its quality improvement.
We express our sincere gratitude and deep appreciation to Dr. Husain Parvez
and Dr. Hayder Mrabet for providing continued technical support. This book
would not have been possible without their support and guidance. We would like
tothankourcolleaguesatSoC-LIP6andtheFPGAteamcolleaguesEmnaAmouri
and Alp Kilic.
Paris, France, February 2012 Umer Farooq
Zied Marrakchi
Habib Mehrez
ix
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Book Motivation and Contributions. . . . . . . . . . . . . . . . . . . . . 3
1.2.1 Exploration Environment for Heterogeneous
Tree-Based FPGA Architectures. . . . . . . . . . . . . . . . . . 5
1.2.1 Exploration of Tree-Based ASIF Architecture. . . . . . . . . 5
1.3 Book Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 FPGA Architectures: An Overview. . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Introduction to FPGAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Programming Technologies. . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.1 SRAM-Based Programming Technology . . . . . . . . . . . . 9
2.2.2 Flash Programming Technology . . . . . . . . . . . . . . . . . . 10
2.2.3 Anti-fuse Programming Technology . . . . . . . . . . . . . . . 10
2.3 Configurable Logic Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 FPGA Routing Architectures. . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4.1 Island-Style Routing Architecture. . . . . . . . . . . . . . . . . 14
2.4.2 Hierarchical Routing Architecture. . . . . . . . . . . . . . . . . 19
2.5 Software Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.5.1 Logic Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.5.2 Technology Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.5.3 Clustering/Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.5.4 Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.5.5 Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.5.6 Timing Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.5.7 Bitstream Generation. . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.6 Research Trends in Reconfigurable Architectures . . . . . . . . . . . 39
2.6.1 Heterogeneous FPGA Architectures. . . . . . . . . . . . . . . . 40
2.6.2 FPGAs to Structured Architectures . . . . . . . . . . . . . . . . 43
2.6.3 Configurable ASIC Cores . . . . . . . . . . . . . . . . . . . . . . 44
xi
xii Contents
2.6.4 Processors Inside FPGAs. . . . . . . . . . . . . . . . . . . . . . . 45
2.6.5 Application Specific FPGAs. . . . . . . . . . . . . . . . . . . . . 45
2.6.6 Time-Multiplexed FPGAs . . . . . . . . . . . . . . . . . . . . . . 46
2.6.7 Asynchronous FPGA Architecture. . . . . . . . . . . . . . . . . 46
2.7 Summary and Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3 Homogeneous Architectures Exploration Environments. . . . . . . . . 49
3.1 Reference FPGA Architectures . . . . . . . . . . . . . . . . . . . . . . . . 50
3.1.1 Mesh-Based FPGA Architecture. . . . . . . . . . . . . . . . . . 50
3.1.2 Tree-Based FPGA Architecture. . . . . . . . . . . . . . . . . . . 52
3.1.3 Comparison with Mesh Model . . . . . . . . . . . . . . . . . . . 60
3.2 Architectures Exploration Environments. . . . . . . . . . . . . . . . . . 60
3.3 Architecture Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.3.1 Architecture Description of Tree-Based Architecture. . . . 61
3.3.2 Architecture Description of Mesh-Based Architecture . . . 61
3.4 Software Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.4.1 Logic Optimization, Mapping and Packing. . . . . . . . . . . 62
3.4.2 Software Flow for Tree-Based Architecture . . . . . . . . . . 63
3.4.3 Software Flow for Mesh-Based Architecture . . . . . . . . . 66
3.4.4 Timing Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.4.5 Area and Delay Models. . . . . . . . . . . . . . . . . . . . . . . . 67
3.5 Experimentation and Analysis. . . . . . . . . . . . . . . . . . . . . . . . . 69
3.5.1 Architectures Optimization Approaches. . . . . . . . . . . . . 69
3.5.2 Effect of LUT and Arity Size on Tree-Based
FPGA Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.5.3 Comparison Between Homogeneous Mesh
and Tree-Based FPGAs . . . . . . . . . . . . . . . . . . . . . . . . 75
3.6 FPGA Hardware Generation. . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.6.1 FPGA Generation Flow. . . . . . . . . . . . . . . . . . . . . . . . 81
3.6.2 FPGA VHDL Model Generation. . . . . . . . . . . . . . . . . . 82
3.6.3 FPGA Layout Generation. . . . . . . . . . . . . . . . . . . . . . . 83
3.7 Summary and Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4 Heterogeneous Architectures Exploration Environments . . . . . . . . 85
4.1 Introduction and Previous Work . . . . . . . . . . . . . . . . . . . . . . . 85
4.2 Reference Heterogeneous FPGA Architectures . . . . . . . . . . . . . 87
4.2.1 Heterogeneous Tree-Based FPGA Architecture. . . . . . . . 87
4.2.2 Heterogeneous Mesh-Based FPGA Architecture . . . . . . . 90
4.3 Architecture Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.3.1 Architecture Description of Heterogeneous
Tree-Based Architecture . . . . . . . . . . . . . . . . . . . . . . . 92
4.3.2 Architecture Description of Heterogeneous
Mesh-Based Architecture. . . . . . . . . . . . . . . . . . . . . . . 95
4.4 Software Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Contents xiii
4.4.1 Parsers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.4.2 Software Flow for Heterogeneous
Tree-Based Architecture . . . . . . . . . . . . . . . . . . . . . . . 100
4.4.3 Software Flow for Heterogeneous
Mesh-Based Architecture. . . . . . . . . . . . . . . . . . . . . . . 101
4.4.4 Area Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.5 Exploration Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.5.1 Exploration Techniques for Heterogeneous
Tree-Based Architecture . . . . . . . . . . . . . . . . . . . . . . . 104
4.5.2 Exploration Techniques for Heterogeneous
Mesh-Based Architecture. . . . . . . . . . . . . . . . . . . . . . . 106
4.6 Experimentation and Analysis. . . . . . . . . . . . . . . . . . . . . . . . . 108
4.6.1 Benchmark Selection. . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.6.2 Experimental Methodology . . . . . . . . . . . . . . . . . . . . . 110
4.6.3 Results Using Individual Experimentation Approach. . . . 111
4.6.4 Results Using Generalized Experimentation Approach. . . 117
4.7 Heterogeneous FPGA Hardware Generation . . . . . . . . . . . . . . . 121
4.8 Summary and Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5 Tree-Based Application Specific Inflexible FPGA . . . . . . . . . . . . . 123
5.1 Introduction and Previous Work . . . . . . . . . . . . . . . . . . . . . . . 123
5.2 Reference FPGA Architectures . . . . . . . . . . . . . . . . . . . . . . . . 125
5.2.1 Reference Tree-Based FPGA Architecture. . . . . . . . . . . 125
5.2.2 Reference Mesh-Based FPGA Architecture . . . . . . . . . . 125
5.3 Software Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.4 ASIF Generation Techniques . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.4.1 ASIF-Normal Partitioning/Placement Normal Routing. . . 127
5.4.2 ASIF-Efficient Partitioning/Placement
Normal Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.4.3 ASIF-Normal Partitioning/Placement
Efficient Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.4.4 ASIF-Efficient Partitioning/Placement
Efficient Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.5 ASIF Area Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.6 Experimental Results and Analysis . . . . . . . . . . . . . . . . . . . . . 133
5.6.1 Effect of Different ASIF Generation Techniques
on Tree-Based Architecture . . . . . . . . . . . . . . . . . . . . . 133
5.6.2 Effect of LUT and Arity Size on Tree-Based ASIF. . . . . 138
5.6.3 Comparison Between Mesh-Based
and Tree-Based ASIFs. . . . . . . . . . . . . . . . . . . . . . . . . 142
5.6.4 Quality Analysis of Tree-Based ASIF . . . . . . . . . . . . . . 144
5.6.5 Quality Comparison Between Mesh-Based
and Tree-Based ASIFs. . . . . . . . . . . . . . . . . . . . . . . . . 146