Table Of ContentAM335x and AMIC110 Sitara™ Processors
Technical Reference Manual
LiteratureNumber:SPRUH73Q
October2011–RevisedDecember2019
Contents
Preface..................................................................................................................................... 173
1 Introduction..................................................................................................................... 174
1.1 AM335xFamily............................................................................................................ 174
1.1.1 DeviceFeatures.................................................................................................. 174
1.1.2 DeviceIdentification............................................................................................. 174
1.2 SiliconRevisionFunctionalDifferencesandEnhancements....................................................... 174
1.2.1 AddedRTCAlarmWakeupforDeepSleepModes.......................................................... 174
1.2.2 ChangedBOOTPIdentifier..................................................................................... 174
1.2.3 ChangedProductStringinUSBDescriptor.................................................................. 175
1.2.4 AddedDPLLPowerSwitchControlandStatusRegisters................................................. 175
1.2.5 AddedControlforCORESRAMLDORetentionMode..................................................... 175
1.2.6 AddedPinMuxOptionsforGPMC_A9toFacilitateRMIIPinMuxing.................................... 175
1.2.7 ChangedPolarityofInputSignalnNMI(PinEXTINTn)..................................................... 175
1.2.8 ChangedDefaultValueofncinandpcinBitsinvtp_ctrlRegister......................................... 176
1.2.9 ChangedDefaultValueofRGMIIModetoNoInternalDelay............................................. 176
1.2.10 ChangedDefaultValueofRMIIClockSource.............................................................. 176
1.2.11 ChangedtheMethodofDeterminingSpeedofOperationDuringEMACBoot........................ 176
1.2.12 AddedEFUSE_SMARegisterforHelpIdentifyingDifferentDeviceVariants.......................... 176
2 MemoryMap.................................................................................................................... 177
2.1 ARMCortex-A8MemoryMap........................................................................................... 177
3 ARMMPUSubsystem ....................................................................................................... 186
3.1 ARMCortex-A8MPUSubsystem...................................................................................... 187
3.1.1 Features........................................................................................................... 188
3.1.2 MPUSubsystemIntegration.................................................................................... 188
3.1.3 MPUSubsystemClockandResetDistribution.............................................................. 189
3.1.4 ARMSubchip..................................................................................................... 192
3.1.5 InterruptController............................................................................................... 193
3.1.6 PowerManagement............................................................................................. 194
3.1.7 ARMProgrammingModel...................................................................................... 196
4 ProgrammableReal-TimeUnitSubsystemandIndustrialCommunicationSubsystem(PRU-
ICSS)............................................................................................................................... 198
4.1 Introduction................................................................................................................ 199
4.1.1 Features........................................................................................................... 200
4.2 Integration.................................................................................................................. 201
4.2.1 PRU-ICSSConnectivityAttributes............................................................................. 202
4.2.2 PRU-ICSSClockandResetManagement................................................................... 202
4.2.3 PRU-ICSSPinList............................................................................................... 203
4.2.4 PRU-ICSSInternalPinmux..................................................................................... 204
4.3 PRU-ICSSMemoryMapOverview..................................................................................... 206
4.3.1 LocalMemoryMap.............................................................................................. 206
4.3.2 GlobalMemoryMap............................................................................................. 207
4.4 FunctionalDescription.................................................................................................... 208
4.4.1 PRUCores........................................................................................................ 208
4.4.2 InterruptController(INTC)...................................................................................... 225
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4.4.3 IndustrialEthernetPeripheral(IEP)........................................................................... 233
4.4.4 UniversalAsynchronousReceiver/Transmitter(UART).................................................... 241
4.4.5 ECAP.............................................................................................................. 254
4.4.6 MII_RT ............................................................................................................ 254
4.4.7 MDIO.............................................................................................................. 273
4.5 Registers................................................................................................................... 274
4.5.1 PRU_ICSS_PRU_CTRLRegisters............................................................................ 274
4.5.2 PRU_ICSS_PRU_DEBUGRegisters......................................................................... 284
4.5.3 PRU_ICSS_INTCRegisters.................................................................................... 349
4.5.4 PRU_ICSS_IEPRegisters...................................................................................... 413
4.5.5 PRU_ICSS_UARTRegisters................................................................................... 464
4.5.6 PRU_ICSS_ECAPRegisters................................................................................... 483
4.5.7 PRU_ICSS_MII_RTRegisters................................................................................. 483
4.5.8 PRU_ICSS_MDIORegisters................................................................................... 503
4.5.9 PRU_ICSS_CFGRegisters.................................................................................... 503
5 GraphicsAccelerator(SGX)............................................................................................... 522
5.0.10 POWERVRSGXMainFeatures.............................................................................. 523
5.0.11 SGX3DFeatures............................................................................................... 524
5.0.12 UniversalScalableShaderEngine(USSE)–KeyFeatures.............................................. 525
5.0.13 UnsupportedFeatures......................................................................................... 525
5.1 Integration.................................................................................................................. 526
5.1.1 SGX530ConnectivityAttributes............................................................................... 526
5.1.2 SGX530ClockandResetManagement...................................................................... 526
5.1.3 SGX530PinList................................................................................................. 527
5.2 FunctionalDescription.................................................................................................... 528
5.2.1 SGXBlockDiagram............................................................................................. 528
5.2.2 SGXElementsDescription..................................................................................... 528
6 Interrupts......................................................................................................................... 530
6.1 FunctionalDescription.................................................................................................... 531
6.1.1 InterruptProcessing ............................................................................................ 532
6.1.2 RegisterProtection.............................................................................................. 533
6.1.3 ModulePowerSaving........................................................................................... 533
6.1.4 ErrorHandling.................................................................................................... 533
6.1.5 InterruptHandling................................................................................................ 533
6.2 BasicProgrammingModel............................................................................................... 534
6.2.1 InitializationSequence.......................................................................................... 534
6.2.2 INTCProcessingSequence.................................................................................... 534
6.2.3 INTCPreemptiveProcessingSequence ..................................................................... 538
6.2.4 InterruptPreemption............................................................................................. 542
6.2.5 ARMA8INTCSpuriousInterruptHandling.................................................................. 542
6.3 ARMCortex-A8Interrupts............................................................................................... 543
6.4 CryptoDMAEvents ...................................................................................................... 547
6.5 PWMEvents............................................................................................................... 549
6.6 InterruptControllerRegisters............................................................................................ 550
6.6.1 INTCRegisters................................................................................................... 550
7 MemorySubsystem.......................................................................................................... 596
7.1 GPMC...................................................................................................................... 597
7.1.1 Introduction....................................................................................................... 597
7.1.2 Integration......................................................................................................... 600
7.1.3 GPMCHigh-LevelProgrammingModelOverview.......................................................... 681
7.1.4 UseCases........................................................................................................ 692
7.1.5 GPMCRegisters................................................................................................. 702
7.2 OCMC-RAM............................................................................................................... 900
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7.2.1 Introduction....................................................................................................... 900
7.2.2 Integration......................................................................................................... 901
7.3 EMIF........................................................................................................................ 902
7.3.1 Introduction....................................................................................................... 902
7.3.2 Integration......................................................................................................... 904
7.3.3 FunctionalDescription........................................................................................... 906
7.3.4 UseCases........................................................................................................ 928
7.3.5 EMIF4DRegisters............................................................................................... 928
7.3.6 DDR2/3/mDDRPHYRegisters................................................................................ 972
7.4 ELM......................................................................................................................... 982
7.4.1 Introduction....................................................................................................... 982
7.4.2 Integration......................................................................................................... 983
7.4.3 FunctionalDescription........................................................................................... 984
7.4.4 BasicProgrammingModel...................................................................................... 987
7.4.5 ELMRegisters.................................................................................................... 992
8 Power,Reset,andClockManagement(PRCM)................................................................... 1197
8.1 Power,Reset,andClockManagement.............................................................................. 1198
8.1.1 Introduction ..................................................................................................... 1198
8.1.2 DevicePower-ManagementArchitectureBuildingBlocks ............................................... 1198
8.1.3 ClockManagement ............................................................................................ 1198
8.1.4 PowerManagement ........................................................................................... 1204
8.1.5 PRCMModuleOverview ..................................................................................... 1215
8.1.6 ClockGenerationandManagement......................................................................... 1217
8.1.7 ResetManagement............................................................................................ 1237
8.1.8 Power-Up/DownSequence................................................................................... 1248
8.1.9 IOState.......................................................................................................... 1249
8.1.10 VoltageandPowerDomains................................................................................ 1249
8.1.11 DeviceModulesandPowerManagementAttributesList ............................................... 1250
8.1.12 ClockModuleRegisters...................................................................................... 1253
8.1.13 PowerManagementRegisters.............................................................................. 1407
9 ControlModule............................................................................................................... 1448
9.1 Introduction............................................................................................................... 1449
9.2 FunctionalDescription.................................................................................................. 1449
9.2.1 ControlModuleInitialization................................................................................... 1449
9.2.2 PadControlRegisters......................................................................................... 1449
9.2.3 EDMAEventMultiplexing..................................................................................... 1451
9.2.4 DeviceControlandStatus.................................................................................... 1451
9.2.5 DDRPHY........................................................................................................ 1457
9.3 Registers................................................................................................................. 1458
9.3.1 CONTROL_MODULERegisters............................................................................. 1458
10 Interconnects ................................................................................................................. 1561
10.1 Introduction............................................................................................................... 1562
10.1.1 Terminology.................................................................................................... 1562
10.1.2 L3Interconnect................................................................................................ 1562
10.1.3 L4Interconnect................................................................................................ 1565
11 EnhancedDirectMemoryAccess(EDMA).......................................................................... 1566
11.1 Introduction............................................................................................................... 1567
11.1.1 EDMA3ControllerBlockDiagram .......................................................................... 1567
11.1.2 Third-PartyChannelController(TPCC)Overview........................................................ 1568
11.1.3 Third-PartyTransferController(TPTC)Overview........................................................ 1570
11.2 Integration................................................................................................................ 1571
11.2.1 Third-PartyChannelController(TPCC)Integration ...................................................... 1571
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11.2.2 Third-PartyTransferController(TPTC)Integration....................................................... 1572
11.3 FunctionalDescription.................................................................................................. 1574
11.3.1 FunctionalOverview.......................................................................................... 1574
11.3.2 TypesofEDMA3Transfers.................................................................................. 1577
11.3.3 ParameterRAM(PaRAM)................................................................................... 1579
11.3.4 InitiatingaDMATransfer..................................................................................... 1591
11.3.5 CompletionofaDMATransfer.............................................................................. 1594
11.3.6 Event,Channel,andPaRAMMapping..................................................................... 1595
11.3.7 EDMA3ChannelControllerRegions....................................................................... 1597
11.3.8 ChainingEDMA3Channels.................................................................................. 1600
11.3.9 EDMA3Interrupts............................................................................................. 1600
11.3.10 MemoryProtection .......................................................................................... 1607
11.3.11 EventQueues................................................................................................ 1611
11.3.12 EDMA3TransferController(EDMA3TC)................................................................. 1613
11.3.13 EventDataflow............................................................................................... 1616
11.3.14 EDMA3Prioritization........................................................................................ 1616
11.3.15 EDMA3OperatingFrequency(ClockControl)........................................................... 1617
11.3.16 ResetConsiderations....................................................................................... 1617
11.3.17 PowerManagement......................................................................................... 1617
11.3.18 EmulationConsiderations.................................................................................. 1617
11.3.19 EDMATransferExamples.................................................................................. 1619
11.3.20 EDMAEvents................................................................................................ 1635
11.4 EDMA3Registers....................................................................................................... 1638
11.4.1 EDMA3CCRegisters......................................................................................... 1638
11.4.2 EDMA3TCRegisters.......................................................................................... 1773
11.5 AppendixA............................................................................................................... 1826
11.5.1 DebugChecklist............................................................................................... 1826
11.5.2 MiscellaneousProgramming/DebugTips.................................................................. 1827
11.5.3 SettingUpaTransfer......................................................................................... 1829
12 TouchscreenController................................................................................................... 1831
12.1 Introduction............................................................................................................... 1832
12.1.1 TSC_ADCFeatures........................................................................................... 1832
12.1.2 UnsupportedTSC_ADC_SSFeatures..................................................................... 1832
12.2 Integration................................................................................................................ 1833
12.2.1 TSC_ADCConnectivityAttributes.......................................................................... 1833
12.2.2 TSC_ADCClockandResetManagement................................................................. 1834
12.2.3 TSC_ADCPinList............................................................................................ 1834
12.3 FunctionalDescription.................................................................................................. 1835
12.3.1 Hardware-SynchronizedorSoftware-Enabled............................................................ 1835
12.3.2 OpenDelayandSampleDelay............................................................................. 1835
12.3.3 AveragingofSamples(1,2,4,8,and16)................................................................. 1835
12.3.4 One-Shot(Single)orContinuousMode ................................................................... 1835
12.3.5 Interrupts....................................................................................................... 1835
12.3.6 DMARequests ................................................................................................ 1836
12.3.7 AnalogFrontEnd(AFE)FunctionalBlockDiagram ..................................................... 1836
12.4 OperationalModes...................................................................................................... 1838
12.4.1 PenCtrlandPenIRQ.......................................................................................... 1839
12.5 TouchscreenControllerRegisters .................................................................................... 1842
12.5.1 TSC_ADC_SSRegisters..................................................................................... 1842
13 LCDController................................................................................................................ 1924
13.1 Introduction............................................................................................................... 1925
13.1.1 PurposeofthePeripheral.................................................................................... 1925
13.1.2 Features........................................................................................................ 1926
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13.2 Integration................................................................................................................ 1927
13.2.1 LCDControllerConnectivityAttributes..................................................................... 1927
13.2.2 LCDControllerClockandResetManagement............................................................ 1928
13.2.3 LCDControllerPinList....................................................................................... 1928
13.3 FunctionalDescription.................................................................................................. 1929
13.3.1 Clocking........................................................................................................ 1929
13.3.2 LCDExternalI/OSignals..................................................................................... 1931
13.3.3 PinMappingandColorAssignments....................................................................... 1931
13.3.4 DMAEngine ................................................................................................... 1932
13.3.5 LIDDController................................................................................................ 1933
13.3.6 RasterController.............................................................................................. 1939
13.3.7 InterruptConditions........................................................................................... 1953
13.3.8 DMA............................................................................................................. 1955
13.3.9 PowerManagement .......................................................................................... 1955
13.4 ProgrammingModel .................................................................................................... 1956
13.4.1 LCDCharacterDisplays...................................................................................... 1956
13.4.2 ActiveMatrixDisplays........................................................................................ 1959
13.4.3 SystemInteraction............................................................................................ 1959
13.4.4 PaletteLookup................................................................................................. 1959
13.4.5 TestLogic...................................................................................................... 1961
13.4.6 DisableandSoftwareResetSequence.................................................................... 1961
13.4.7 PrecedenceOrderforDeterminingFrameBufferType.................................................. 1962
13.5 Registers................................................................................................................. 1963
13.5.1 LCDRegisters................................................................................................. 1963
14 EthernetSubsystem........................................................................................................ 2000
14.1 Introduction............................................................................................................... 2001
14.1.1 Features........................................................................................................ 2001
14.1.2 UnsupportedFeatures........................................................................................ 2002
14.2 Integration................................................................................................................ 2003
14.2.1 EthernetSwitchConnectivityAttributes.................................................................... 2004
14.2.2 EthernetSwitchClockandResetManagement .......................................................... 2005
14.2.3 EthernetSwitchPinList...................................................................................... 2006
14.2.4 EthernetSwitchRMIIClockingDetails..................................................................... 2006
14.2.5 GMIIInterfaceSignalConnectionsandDescriptions .................................................... 2007
14.2.6 RMIISignalConnectionsandDescriptions................................................................ 2009
14.2.7 RGMIISignalConnectionsandDescriptions.............................................................. 2011
14.3 FunctionalDescription.................................................................................................. 2013
14.3.1 CPSW_3GSubsystem....................................................................................... 2013
14.3.2 CPSW_3G...................................................................................................... 2018
14.3.3 EthernetMacSliver(CPGMAC_SL) ....................................................................... 2061
14.3.4 CommandIDLE ............................................................................................... 2063
14.3.5 RMIIInterface.................................................................................................. 2063
14.3.6 RGMIIInterface................................................................................................ 2064
14.3.7 CommonPlatformTimeSync(CPTS) ..................................................................... 2065
14.3.8 MDIO............................................................................................................ 2070
14.4 SoftwareOperation ..................................................................................................... 2073
14.4.1 TransmitOperation............................................................................................ 2073
14.4.2 ReceiveOperation............................................................................................ 2075
14.4.3 InitializingtheMDIOModule................................................................................. 2076
14.4.4 WritingDatatoaPHYRegister............................................................................. 2076
14.4.5 ReadingDatafromaPHYRegister ........................................................................ 2077
14.4.6 InitializationandConfigurationofCPSW .................................................................. 2077
14.5 EthernetSubsystemRegisters........................................................................................ 2078
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14.5.1 CPSW_ALERegisters........................................................................................ 2078
14.5.2 CPSW_CPDMARegisters................................................................................... 2093
14.5.3 CPSW_CPTSRegisters...................................................................................... 2148
14.5.4 CPSW_STATSRegisters.................................................................................... 2161
14.5.5 CPDMA_STATERAMRegisters............................................................................. 2161
14.5.6 CPSW_PORTRegisters ..................................................................................... 2195
14.5.7 CPSW_SLRegisters.......................................................................................... 2250
14.5.8 CPSW_SSRegisters......................................................................................... 2264
14.5.9 CPSW_WRRegisters ........................................................................................ 2277
14.5.10 MDIORegisters.............................................................................................. 2313
15 Pulse-WidthModulationSubsystem(PWMSS).................................................................... 2324
15.1 Pulse-WidthModulationSubsystem(PWMSS)..................................................................... 2325
15.1.1 Introduction..................................................................................................... 2325
15.1.2 Integration...................................................................................................... 2327
15.1.3 PWMSSRegisters............................................................................................ 2329
15.2 EnhancedPWM(ePWM)Module..................................................................................... 2334
15.2.1 Introduction..................................................................................................... 2334
15.2.2 FunctionalDescription........................................................................................ 2338
15.2.3 UseCases ..................................................................................................... 2409
15.2.4 EPWMRegisters.............................................................................................. 2433
15.3 EnhancedCapture(eCAP)Module................................................................................... 2469
15.3.1 Introduction..................................................................................................... 2469
15.3.2 FunctionalDescription........................................................................................ 2470
15.3.3 UseCases ..................................................................................................... 2479
15.3.4 Registers....................................................................................................... 2495
15.4 EnhancedQuadratureEncoderPulse(eQEP)Module............................................................ 2511
15.4.1 Introduction..................................................................................................... 2511
15.4.2 FunctionalDescription........................................................................................ 2514
15.4.3 EQEPRegisters............................................................................................... 2532
16 UniversalSerialBus(USB)............................................................................................... 2559
16.0.4 Acronyms,Abbreviations,andDefinitions................................................................. 2560
16.0.5 UnsupportedUSBOTGandPHYFeatures............................................................... 2562
16.1 Integration................................................................................................................ 2563
16.1.1 USBConnectivityAttributes ................................................................................. 2563
16.1.2 USBClockandResetManagement........................................................................ 2564
16.1.3 USBPinList ................................................................................................... 2564
16.1.4 USBGPIODetails............................................................................................. 2564
16.1.5 USBUnbondedPHYPads................................................................................... 2565
16.2 FunctionalDescription.................................................................................................. 2566
16.2.1 VBUSVoltageSourcingControl ............................................................................ 2566
16.2.2 Pullup/PullDownResistors................................................................................... 2566
16.2.3 RoleAssumingMethod....................................................................................... 2567
16.2.4 Clock,PLL,andPHYInitialization.......................................................................... 2567
16.2.5 IndexedandNon-IndexedRegisterSpaces............................................................... 2567
16.2.6 DynamicFIFOSizing......................................................................................... 2567
16.2.7 USBControllerHostandPeripheralModesOperation.................................................. 2568
16.2.8 ProtocolDescription(s)....................................................................................... 2570
16.2.9 CommunicationsPortProgrammingInterface(CPPI)4.1DMA........................................ 2603
16.2.10 USB2.0TestModes........................................................................................ 2627
16.3 SupportedUseCases.................................................................................................. 2629
16.4 USBRegisters........................................................................................................... 2630
16.4.1 USBSSRegisters............................................................................................. 2630
16.4.2 USB0_CTRLRegisters....................................................................................... 2675
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16.4.3 USB1_CTRLRegisters....................................................................................... 2725
16.4.4 USB2PHYRegisters.......................................................................................... 2773
16.4.5 CPPI_DMARegisters......................................................................................... 2798
16.4.6 CPPI_DMA_SCHEDULERRegisters....................................................................... 2954
16.4.7 QUEUE_MGRRegisters..................................................................................... 2957
17 InterprocessorCommunication......................................................................................... 4108
17.1 Mailbox ................................................................................................................... 4109
17.1.1 Introduction..................................................................................................... 4109
17.1.2 ProgrammingGuide .......................................................................................... 4115
17.1.3 MAILBOXRegisters .......................................................................................... 4118
17.2 Spinlock................................................................................................................... 4179
17.2.1 SPINLOCKRegisters......................................................................................... 4179
18 MultimediaCard (MMC).................................................................................................... 4217
18.1 Introduction............................................................................................................... 4218
18.1.1 MMCHSFeatures............................................................................................. 4218
18.1.2 UnsupportedMMCHSFeatures............................................................................. 4218
18.2 Integration................................................................................................................ 4219
18.2.1 MMCHSConnectivityAttributes............................................................................. 4220
18.2.2 MMCHSClockandResetManagement................................................................... 4221
18.2.3 MMCHSPinList............................................................................................... 4221
18.3 FunctionalDescription.................................................................................................. 4223
18.3.1 MMC/SD/SDIOFunctionalModes.......................................................................... 4223
18.3.2 Resets.......................................................................................................... 4229
18.3.3 PowerManagement .......................................................................................... 4230
18.3.4 InterruptRequests ............................................................................................ 4233
18.3.5 DMAModes ................................................................................................... 4235
18.3.6 ModeSelection................................................................................................ 4238
18.3.7 BufferManagement........................................................................................... 4238
18.3.8 TransferProcess.............................................................................................. 4241
18.3.9 TransferorCommandStatusandErrorReporting....................................................... 4242
18.3.10 AutoCommand12Timings................................................................................ 4247
18.3.11 TransferStop................................................................................................. 4249
18.3.12 OutputSignalsGeneration................................................................................. 4250
18.3.13 CardBootModeManagement............................................................................. 4252
18.3.14 CE-ATACommandCompletionDisableManagement................................................. 4254
18.3.15 TestRegisters................................................................................................ 4254
18.3.16 MMC/SD/SDIOHardwareStatusFeatures .............................................................. 4255
18.4 Low-LevelProgrammingModels...................................................................................... 4256
18.4.1 SurroundingModulesGlobalInitialization ................................................................. 4256
18.4.2 MMC/SD/SDIOControllerInitializationFlow .............................................................. 4256
18.4.3 OperationalModesConfiguration........................................................................... 4259
18.5 MultimediaCardRegisters............................................................................................. 4261
18.5.1 MULTIMEDIA_CARDRegisters............................................................................. 4261
19 UniversalAsynchronousReceiver/Transmitter(UART)........................................................ 4318
19.1 Introduction............................................................................................................... 4319
19.1.1 UARTModeFeatures........................................................................................ 4319
19.1.2 IrDAModeFeatures.......................................................................................... 4319
19.1.3 CIRModeFeatures........................................................................................... 4319
19.1.4 UnsupportedUARTFeatures................................................................................ 4319
19.2 Integration................................................................................................................ 4321
19.2.1 UARTConnectivityAttributes................................................................................ 4321
19.2.2 UARTClockandResetManagement...................................................................... 4322
19.2.3 UARTPinList.................................................................................................. 4324
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19.3 FunctionalDescription.................................................................................................. 4325
19.3.1 BlockDiagram................................................................................................. 4325
19.3.2 ClockConfiguration........................................................................................... 4326
19.3.3 SoftwareReset................................................................................................ 4326
19.3.4 PowerManagement .......................................................................................... 4326
19.3.5 InterruptRequests ............................................................................................ 4328
19.3.6 FIFOManagement............................................................................................ 4331
19.3.7 ModeSelection................................................................................................ 4339
19.3.8 ProtocolFormatting........................................................................................... 4345
19.4 UART/IrDA/CIRBasicProgrammingModel......................................................................... 4368
19.4.1 UARTProgrammingModel.................................................................................. 4368
19.4.2 IrDAProgrammingModel.................................................................................... 4374
19.5 UARTRegisters......................................................................................................... 4377
19.5.1 UARTRegisters............................................................................................... 4377
20 Timers........................................................................................................................... 4435
20.1 DMTimer.................................................................................................................. 4436
20.1.1 Introduction..................................................................................................... 4436
20.1.2 Integration...................................................................................................... 4438
20.1.3 FunctionalDescription........................................................................................ 4442
20.1.4 UseCases ..................................................................................................... 4451
20.1.5 TIMERRegisters.............................................................................................. 4451
20.2 DMTimer1ms............................................................................................................ 4470
20.2.1 Introduction..................................................................................................... 4470
20.2.2 Integration...................................................................................................... 4472
20.2.3 FunctionalDescription........................................................................................ 4474
20.2.4 DMTIMER_1MSRegisters................................................................................... 4482
20.3 RTC_SS.................................................................................................................. 4506
20.3.1 Introduction..................................................................................................... 4506
20.3.2 Integration...................................................................................................... 4507
20.3.3 FunctionalDescription........................................................................................ 4509
20.3.4 UseCases ..................................................................................................... 4517
20.3.5 RTCRegisters................................................................................................. 4517
20.4 WATCHDOG............................................................................................................. 4555
20.4.1 Introduction..................................................................................................... 4555
20.4.2 Integration...................................................................................................... 4556
20.4.3 FunctionalDescription........................................................................................ 4558
20.4.4 WatchdogRegisters.......................................................................................... 4565
21 I2C................................................................................................................................ 4583
21.1 Introduction............................................................................................................... 4584
21.1.1 I2CFeatures................................................................................................... 4584
21.1.2 UnsupportedI2CFeatures................................................................................... 4584
21.2 Integration................................................................................................................ 4585
21.2.1 I2CConnectivityAttributes................................................................................... 4585
21.2.2 I2CClockandResetManagement......................................................................... 4586
21.2.3 I2CPinList..................................................................................................... 4586
21.3 FunctionalDescription.................................................................................................. 4587
21.3.1 FunctionalBlockDiagram.................................................................................... 4587
21.3.2 I2CMaster/SlaveContollerSignals......................................................................... 4587
21.3.3 I2CReset....................................................................................................... 4588
21.3.4 DataValidity ................................................................................................... 4589
21.3.5 START&STOPConditions.................................................................................. 4590
21.3.6 I2COperation.................................................................................................. 4590
21.3.7 Arbitration...................................................................................................... 4592
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21.3.8 I2CClockGenerationandI2CClockSynchronization................................................... 4592
21.3.9 Prescaler(SCLK/ICLK)....................................................................................... 4593
21.3.10 NoiseFilter ................................................................................................... 4593
21.3.11 I2CInterrupts................................................................................................. 4593
21.3.12 DMAEvents.................................................................................................. 4594
21.3.13 InterruptandDMAEvents.................................................................................. 4594
21.3.14 FIFOManagement .......................................................................................... 4594
21.3.15 HowtoProgramI2C......................................................................................... 4599
21.3.16 I2CBehaviorDuringEmulation............................................................................ 4600
21.4 I2CRegisters............................................................................................................ 4601
21.4.1 I2CRegisters.................................................................................................. 4601
22 MultichannelAudioSerialPort(McASP)............................................................................ 4652
22.1 Introduction............................................................................................................... 4653
22.1.1 PurposeofthePeripheral.................................................................................... 4653
22.1.2 Features........................................................................................................ 4653
22.1.3 ProtocolsSupported ......................................................................................... 4654
22.1.4 UnsupportedMcASPFeatures.............................................................................. 4654
22.2 Integration................................................................................................................ 4655
22.2.1 McASPConnectivityAttributes.............................................................................. 4655
22.2.2 McASPClockandResetManagement.................................................................... 4656
22.2.3 McASPPinList................................................................................................ 4656
22.3 FunctionalDescription.................................................................................................. 4657
22.3.1 Overview ....................................................................................................... 4657
22.3.2 FunctionalBlockDiagram.................................................................................... 4658
22.3.3 IndustryStandardComplianceStatement................................................................. 4661
22.3.4 DefinitionofTerms............................................................................................ 4665
22.3.5 ClockandFrameSyncGenerators......................................................................... 4667
22.3.6 SignalDescriptions............................................................................................ 4671
22.3.7 PinMultiplexing................................................................................................ 4671
22.3.8 TransferModes................................................................................................ 4672
22.3.9 GeneralArchitecture.......................................................................................... 4679
22.3.10 Operation..................................................................................................... 4683
22.3.11 ResetConsiderations....................................................................................... 4700
22.3.12 SetupandInitialization...................................................................................... 4700
22.3.13 Interrupts...................................................................................................... 4705
22.3.14 EDMAEventSupport ....................................................................................... 4707
22.3.15 PowerManagement......................................................................................... 4709
22.3.16 EmulationConsiderations.................................................................................. 4709
22.4 Registers................................................................................................................. 4710
22.4.1 MCASPRegisters............................................................................................. 4710
23 ControllerAreaNetwork(CAN)......................................................................................... 4772
23.1 Introduction............................................................................................................... 4773
23.1.1 DCANFeatures................................................................................................ 4773
23.1.2 UnsupportedDCANFeatures............................................................................... 4773
23.2 Integration................................................................................................................ 4774
23.2.1 DCANConnectivityAttributes............................................................................... 4774
23.2.2 DCANClockandResetManagement...................................................................... 4775
23.2.3 DCANPinList................................................................................................. 4775
23.3 FunctionalDescription.................................................................................................. 4776
23.3.1 CANCore...................................................................................................... 4776
23.3.2 MessageHandler ............................................................................................. 4777
23.3.3 MessageRAM................................................................................................. 4777
23.3.4 MessageRAMInterface...................................................................................... 4777
10 Contents SPRUH73Q–October2011–RevisedDecember2019
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