TAS6424-Q1 75-W, 2-MHz Digital Input 4-Channel Automotive Class-D Audio Amp datasheet

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TAS6424-Q1
SLOS870B–SEPTEMBER2016–REVISEDOCTOBER2017
TAS6424-Q1 75-W, 2-MHz Digital Input 4-Channel Automotive Class-D Audio Amplifier
2
With Load-Dump Protection and I C Diagnostics
1 Features 2 Applications
• AdvancedLoadDiagnostics • AutomotiveHeadUnits
1
– RunswithoutInputClocks • AutomotiveExternalAmplifierModules
– ACDiagnosticforTweeterDetectionwith
3 Description
ImpedanceandPhaseResponse
The TAS6424-Q1 device is a Four-channel digital-
• EasytomeetCISPR25-L5EMCSpecification
input Class-D audio amplifier that implements a 2.1
• QualifiedforAutomotiveApplications
MHz PWM switching frequency that enables a cost-
• AudioInputs optimized solution in a very small PCB size, full
– 4ChannelI2Sor4/8-ChannelTDMInput operation down to 4.5 V for start/stop events, and
exceptional sound quality with up to 40 kHz audio
– InputSampleRates:44.1kHz,48kHz,96kHz
bandwidth
– InputFormats:16-bitto32-bitI2S,andTDM
The TAS6424-Q1 Class-D audio amplifier is designed
• AudioOutputs
for use in automotive head units and external
– Four-ChannelBridge-TiedLoad(BTL),With amplifier modules. The device provides four channels
OptionofParallelBTL(PBTL) at 27 W into 4 Ω at 10% THD+N and 45 W into 2 Ω
at 10% THD+N from a 14.4-V supply and 75 W into 4
– Upto2.1-MHzOutputSwitchingFrequency
Ω at 10% THD+N from a 25-V supply. The Class-D
– 75W,10%THDInto4 Ωat25V
topology dramatically improves efficiency over
– 45W,10%THDInto2 Ωat14.4V traditional linear amplifier solutions. The output
– 150W,10%THDInto2 Ω at25VPBTL switching frequency can be set either above the AM
band, which eliminates the AM-band interference and
• AudioPerformanceInto4Ω at14.4V
reduces output filter size and cost, or below AM band
– THD+N < 0.03%at1W tooptimizeefficiency.
– 42-µV OutputNoise
RMS For a pin compatible two-channel amplifier, see the
– –90-dBCrosstalk TAS6422-Q1
• LoadDiagnostics
The device is offered in a 56-pin HSSOP
– Output OpenandShortedLoad PowerPAD™ package with the exposed thermal pad
up.
– Output-to-BatteryorGroundShorts
– LineOutputDetectionUpto6kΩ DeviceInformation(1)
– Host-IndependentOperation
PARTNUMBER PACKAGE BODYSIZE(NOM)
– ProgrammabilityforFlexibleProductionLine
TAS6424-Q1 HSSOP(56) 18.41mm×7.49mm
Testing
(1) For all available packages, see the orderable addendum at
• Protection theendofthedatasheet.
– Output CurrentLimiting
PCBAREA
– Output ShortProtection
– 40-VLoadDump
– OpenGroundandPowerTolerant
– DCOffset
– Overtemperature
m
m
– UndervoltageandOvervoltage 2
2
• GeneralOperation
– 4.5-Vto26.4-VSupplyvoltage
– I2CControlWith4AddressOptions
– ClipDetectionandThermalWarning
27 mm
25-W 4-channel
5.9 cm2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.
TAS6424-Q1
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Table of Contents
1 Features.................................................................. 1 9.4 DeviceFunctionalModes........................................28
2 Applications........................................................... 1 9.5 Programming...........................................................28
3 Description............................................................. 1 9.6 RegisterMaps.........................................................32
4 RevisionHistory..................................................... 2 10 ApplicationandImplementation........................ 48
10.1 ApplicationInformation..........................................48
5 DeviceComparisonTable..................................... 3
10.2 TypicalApplications..............................................49
6 PinConfigurationandFunctions......................... 4
11 PowerSupplyRecommendations..................... 55
7 Specifications......................................................... 6
12 Layout................................................................... 55
7.1 AbsoluteMaximumRatings......................................6
12.1 LayoutGuidelines.................................................55
7.2 ESDRatings..............................................................6
12.2 LayoutExample....................................................57
7.3 RecommendedOperatingConditions.......................7
12.3 ThermalConsiderations........................................57
7.4 ThermalInformation..................................................7
13 DeviceandDocumentationSupport................. 58
7.5 ElectricalCharacteristics...........................................7
7.6 TimingRequirements..............................................10 13.1 DocumentationSupport........................................58
7.7 TypicalCharacteristics............................................11 13.2 ReceivingNotificationofDocumentationUpdates58
13.3 CommunityResources..........................................58
8 ParametermeasurementInformation................16
13.4 Trademarks...........................................................58
9 Detaileddescription............................................. 17
13.5 ElectrostaticDischargeCaution............................58
9.1 Overview.................................................................17
13.6 Glossary................................................................58
9.2 FunctionalBlockDiagram.......................................17
14 Mechanical,Packaging,andOrderable
9.3 FeatureDescription.................................................18
Information........................................................... 59
4 Revision History
NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion.
ChangesfromRevisionA(October2016)toRevisionB Page
• ChangedtheFeaturesandDescriptionsectionsforbetterProductFoldervisibility.............................................................. 1
ChangesfromOriginal(September2016)toRevisionA Page
• Releasedthefullversionofthedatasheet ........................................................................................................................... 1
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5 Device Comparison Table
PART CHANNEL POWER-SUPPLY OUTPUTCURRENT MAXIMUMPWM
INPUTTYPE
NUMBER COUNT VOLTAGERANGE LIMIT FREQUENCY
TAS6424-Q1 Digital 4 4.5Vto26.4V 6.5A 2.1MHz
TAS5414C-Q1 Analog,Single-Ended 4 5.6Vto24V 12.7A 500kHz
TAS5424C-Q1 Analog,Differential 4 5.6vto24V 12.7A 500kHz
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6 Pin Configuration and Functions
DKQPackage
56-PinHSSOPWithExposedThermalPad
TopView
GND 1 56 PVDD
PVDD 2 55 PVDD
VBAT 3 54 BST_4P
AREF 4 53 OUT_4P
VREG 5 52 GND
VCOM 6 51 OUT_4M
AVSS 7 50 BST_4M
AVDD 8 49 GND
GVDD 9 48 BST_3P
GVDD 10 47 OUT_3P
GND 11 46 GND
MCLK 12 45 OUT_3M
SCLK 13 44 BST_3M
FSYNC 14 43 PVDD
Thermal
SDIN1 15 Pad 42 PVDD
SDIN2 16 41 BST_2P
GND 17 40 OUT_2P
GND 18 39 GND
VDD 19 38 OUT_2M
SCL 20 37 BST_2M
SDA 21 36 GND
I2C_ADDR0 22 35 BST_1P
I2C_ADDR1 23 34 OUT_1P
STANDBY 24 33 GND
MUTE 25 32 OUT_1M
FAULT 26 31 BST_1M
WARN 27 30 PVDD
GND 28 29 PVDD
Not to scale
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PinFunctions
PIN
TYPE(1) DESCRIPTION
NAME NO.
AREF 4 PWR VREGandVCOMbypasscapacitorreturn
AVDD 8 PWR Voltageregulatorbypass
AVSS 7 PWR AVDDbypasscapacitorreturn
BST_1M 31 PWR Bootstrapcapacitorconnectionpinsforhigh-sidegatedriver
BST_1P 35 PWR Bootstrapcapacitorconnectionpinsforhigh-sidegatedriver
BST_2M 37 PWR Bootstrapcapacitorconnectionpinsforhigh-sidegatedriver
BST_2P 41 PWR Bootstrapcapacitorconnectionpinsforhigh-sidegatedriver
BST_3M 44 PWR Bootstrapcapacitorconnectionpinsforhigh-sidegatedriver
BST_3P 48 PWR Bootstrapcapacitorconnectionpinsforhigh-sidegatedriver
BST_4M 50 PWR Bootstrapcapacitorconnectionpinsforhigh-sidegatedriver
BST_4P 54 PWR Bootstrapcapacitorconnectionpinsforhigh-sidegatedriver
FAULT 26 DO Reportsafault(activelow,opendrain),100-kΩinternalpullupresistor
FSYNC 14 DI Audioframeclockinput
1
11
17
18
28
GND 33 GND Ground
36
39
46
49
52
9 Gatedrivevoltageregulatorforchannel3and4,derivedfromVBATinputpin.
GVDD PWR
10 Gatedrivevoltageregulatorforchannel1and2,derivedfromVBATinputpin.
I2C_ADDR0 22
DI I2Caddresspins
I2C_ADDR1 23
MCLK 12 DI Audiomasterclockinput
MUTE 25 DI Mutesthedeviceoutputs(activelow),100-kΩinternalpulldownresistor
OUT_1M 32 NO Negativeoutputforthechannel
OUT_1P 34 PO Positiveoutputforthechannel
OUT_2M 38 NO Negativeoutputforthechannel
OUT_2P 40 PO Positiveoutputforthechannel
OUT_3M 45 NO Negativeoutputforthechannel
OUT_3P 47 PO Positiveoutputforthechannel
OUT_4M 51 NO Negativeoutputforthechannel
OUT_4P 53 PO Positiveoutputforthechannel
2
29
30
PVDD 42 PWR PVDDvoltageinput(canbeconnectedtobattery)
43
55
56
(1) GND=ground,PWR=power,PO=positiveoutput,NO=negativeoutput,DI=digitalinput,DO=digitaloutput,DI/O=digitalinput
andoutput,NC=noconnection
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PinFunctions (continued)
PIN
TYPE(1) DESCRIPTION
NAME NO.
SCL 20 DI I2Cclockinput
SCLK 13 DI Audiobitandserialclockinput
SDA 21 DI/O I2Cdatainputandoutput
SDIN1 15 DI TDMdatainputandaudioI2Sdatainputforchannels1and2
SDIN2 16 DI AudioI2Sdatainputforchannels3and4
STANDBY 24 DI Enableslowpowerstandbystate(activeLow),100-kΩinternalpulldownresistor
VBAT 3 PWR Batteryvoltageinput
VCOM 6 PWR Biasvoltage
VDD 19 PWR 3.3-Vexternalsupplyvoltage
VREG 5 PWR Voltageregulatorbypass
WARN 27 DO Clipandovertemperaturewarning(activelow,opendrain),100-kΩinternalpullupresistor
Providesbothelectricalandthermalconnectionforthedevice.Heatsinkmustbeconnectedto
ThermalPad — GND
GND.
7 Specifications
7.1 Absolute Maximum Ratings
overoperatingfree-airtemperaturerange(unlessotherwisenoted)
MIN MAX UNIT
PVDD,VBAT DCsupplyvoltagerelativetoGND –0.3 30 V
V Transientsupplyvoltage:PVDD,VBAT t≤400msexposure –1 40 V
MAX
V Supply-voltageramprate:PVDD,VBAT 75 V/ms
RAMP
VDD DCsupplyvoltagerelativetoGND –0.3 3.5 V
I Maximumcurrentperpin(PVDD,VBAT,OUT_xP,OUT_xM,GND) 8 A
MAX
I PulsedsupplycurrentperPVDDpin(oneshot) t<100ms 12 A
MAX_PULSED
Inputvoltageforlogicpins(SCL,SDA,SDIN1,SDIN2,MCLK,BCLK,LRCLK,MUTE,
V –0.3 VDD+0.5 V
LOGIC STANDBY,I2C_ADDRx)
V MaximumvoltagebetweenGNDpins –0.3 0.3 V
GND
T Maximumoperatingjunctiontemperature –55 150 °C
J
T Storagetemperature –55 150 °C
stg
7.2 ESD Ratings
VALUE UNIT
Human-bodymodel(HBM),perAECQ100–002(1) ±3000
Electrostatic
V Allpins ±500 V
(ESD) discharge Charged-devicemodel(CDM),perAECQ100–011
Cornerpins(1,28,29and56) ±1000
(1) AECQ100–002indicatesthatHBMstressingshallbeinaccordancewiththeANSI/ESDA/JEDECJS–001specification.
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7.3 Recommended Operating Conditions
MIN NOM MAX UNIT
PVDD OutputFETsupplyvoltage RelativetoGND 4.5 26.4 V
VBAT Batterysupplyvoltageinput RelativetoGND 4.5 14.4 18 V
VDD DClogicsupply RelativetoGND 3.0 3.3 3.5 V
TA Ambienttemperature –40 125 °C
Anadequatethermaldesignis
TJ Junctiontemperature required –40 150 °C
BTLMode 2 4
RL Nominalspeakerloadimpedance Ω
PBTLMode 1 2
RPU_I2C I2CpullupresistanceonSDAandSCLpins 1 4.7 10 kΩ
CBypass Externalcapacitanceonbypasspins Pin2,3,5,6,8,9,10,19 1 µF
COUT ExternalcapacitancetoGNDonOUTpins LimitsetbyDC-diagnostictiming 1 3.3 µF
LO Outputfilterinductance MinimuminductanceatISDcurrent 1 µH
levels
7.4 Thermal Information
TAS6424-Q1(2) TAS6424-Q1(3)
THERMALMETRIC(1) DKQ(HSSOP) DKQ(HSSOP) UNIT
56PINS 56PINS
R Junction-to-ambientthermalresistance — — °C/W
θJA
R Junction-to-case(top)thermalresistance 0.7 1.1 °C/W
θJC(top)
R Junction-to-boardthermalresistance — — °C/W
θJB
ψ Junction-to-topcharacterizationparameter — — °C/W
JT
ψ Junction-to-boardcharacterizationparameter 10 10 °C/W
JB
R Junction-to-case(bottom)thermalresistance — — °C/W
θJC(bot)
(1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication
report(SPRA953).
(2) JEDECStandard4LayerPCB.
(3) MeasuredusingtheTAS6424-Q1EVMlayoutandheatsink.Thedeviceisnotintendedtobeusedwithoutaheatsink.
7.5 Electrical Characteristics
Testconditions(unlessotherwisenoted):T =25°C,PVDD=VBAT=14.4V,VDD=3.3V,R =4Ω,P =1W/ch,ƒ=1
C L out
kHz,f =2.11MHz,AES17Filter,defaultI2Csettings,seeFigure79andFigure82
SW
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
OPERATINGCURRENT
IPVDD_IDLE PVDDidlecurrent Allchannelsplaying,noaudioinput 75 90 mA
IVBAT_IDLE VBATidlecurrent Allchannelsplaying,noaudioinput 90 100 mA
IPVDD_STBY PVDDstandbycurrent STANDBYActive,VDD=0V 1 10 μA
IVBAT_STBY VBATstandbycurrent STANDBYActive,VDD=0V 4 10 μA
IVDD VDDsupplycurrent Allchannelsplaying,–60-dBsignal 15 18 mA
OUTPUTPOWER
4Ω,PVDD=14.4V,THD+N=1%,TC=75°C 20 22
4Ω,PVDD=14.4V,THD+N=10%,TC=75°C 25 27
2Ω,PVDD=14.4V,THD+N=1%,TC=75°C 38 40
PO_BTL Outputpowerperchannel,BTL W
2Ω,PVDD=14.4V,THD+N=10%,TC=75°C 42 45
4Ω,PVDD=25V,THD+N=1%,TC=75°C 50 55
4Ω,PVDD=25V,THD+N=10%,TC=75°C 70 75
2Ω,PVDD=14.4V,THD+N=1%,TC=75°C 35 40
2Ω,PVDD=14.4V,THD+N=10%,TC=75°C 45 50
Outputpowerperchannelinparallelmode, 1Ω,PVDD=14.4V,THD+N=1%,TC=75°C 72 80
PO_PBTL PBTL 1Ω,PVDD=14.4V,THD+N=10%,TC=75°C 80 90 W
2Ω,PVDD=25V,THD+N=1%,TC=75°C 98 120
2Ω,PVDD=25V,THD+N=10%,TC=75°C 138 150
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Electrical Characteristics (continued)
Testconditions(unlessotherwisenoted):T =25°C,PVDD=VBAT=14.4V,VDD=3.3V,R =4Ω,P =1W/ch,ƒ=1
C L out
kHz,f =2.11MHz,AES17Filter,defaultI2Csettings,seeFigure79andFigure82
SW
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
4channelsoperating,25-Woutputpower/ch4-Ωload,PVDD
EFFP Powerefficiency =14.4V,TC=25°C,includingindcutorlosses(1) 86%
AUDIOPERFORMANCE
Zeroinput,A-weighting,gainlevel1,PVDD=14.4V 42
Zeroinput,A-weighting,gainlevel2,PVDD=14.4V 55
Vn Outputnoisevoltage μV
Zeroinput,A-weighting,gainlevel3,PVDD=18V 67
Zeroinput,A-weighting,gainlevel4,PVDD=25V 85
Gainlevel1,Register0x01,bit1-0=00 7.5
Gainlevel2,Register0x01,bit1-0=01 15
GAIN Peakoutputvoltage/dBFS V/FS
Gainlevel3,Register0x01,bit1-0=10 21
Gainlevel4,Register0x01,bit1-0=11 29
Crosstalk Channelcrosstalk PVDD=14.4Vdc+1VRMS,ƒ=1kHz –90 –75 dB
PSRR Power-supplyrejectionratio PVDD=14.4Vdc+1VRMS,ƒ=1kHz 75 dB
0.05
THD+N Totalharmonicdistortion+noise 0.02%
%
GCH Channel-to-channelgainvariation –0.5 0 0.5 dB
LINEOUTPUTPERFORMANCE
Vn_LINEOUT LINEoutputnoisevoltage Zeroinput,A-weighting,channelsettoLINEMODE 42 μV
VO_LINEOUT LINEoutputvoltage 0-dBinput,channelsettoLINEMODE 5.5 VRMS
0.03
THD+N Lineoutputtotalharmonicdistortion+noise VO=2VRMS,channelsettoLINEMODE 0.01% %
DIGITALINPUTPINS
VIH Inputlogiclevelhigh 70 %VDD
VIL Inputlogiclevellow 30 %VDD
IIH Inputlogiccurrent,high VI=VDD 15 µA
IIL Inputlogiccurrent,low VI=0 –15 µA
PWMOUTPUTSTAGE
RDS(on) FETdrain-to-sourceresistance Notincludingbondwireandpackageresistance 90 mΩ
OVERVOLTAGE(OV)PROTECTION
VPVDD_OV PVDDovervoltageshutdown 27.0 27.8 28.8 V
VPVDD_OV_HY PVDDovervoltageshutdownhysteresis 0.8 V
S
VVBAT_OV VBATovervoltageshutdown 19.3 20 22 V
VVBAT_OV_HY VBATovervoltageshutdownhysteresis 0.6 V
S
UNDERVOLTAGE(UV)PROTECTION
VBATUV VBATundervoltageshutdown 4 4.5 V
VBATUV_HYS VBATundervoltageshutdownhysteresis 0.2 V
PVDDUV PVDDundervoltageshutdown 4 4.5 V
PVDDUV_HY PVDDundervoltageshutdownhysteresis 0.2 V
S
BYPASSVOLTAGES
VGVDD Gatedrivebypasspinvoltage 7 V
VAVDD Analogbypasspinvoltage 6 V
VVCOM Commonbypasspinvoltage 2.5 V
VVREG Regulatorbypasspinvoltage 5.5 V
POWER-ONRESET(POR)
VPOR VDDvoltageforPOR 2.1 2.7 V
VPOR_HY VDDPORrecoveryhysteresisvoltage 0.5 V
OVERTEMPERATURE(OT)PROTECTION
OTW(i) Channelovertemperaturewarning 150 °C
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Electrical Characteristics (continued)
Testconditions(unlessotherwisenoted):T =25°C,PVDD=VBAT=14.4V,VDD=3.3V,R =4Ω,P =1W/ch,ƒ=1
C L out
kHz,f =2.11MHz,AES17Filter,defaultI2Csettings,seeFigure79andFigure82
SW
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
OTSD(i) Channelovertemperatureshutdown 175 °C
OTW Globaljunctionovertemperaturewarning Setbyregister0x01bit5-6,defaultvalue 130 °C
OTSD Globaljunctionovertemperatureshutdown 160 °C
OTHYS Overtemperaturehysteresis 15 °C
LOADOVERCURRENTPROTECTION
OCLevel1 4 4.8
ILIM Overcurrentcycle-by-cyclelimit A
OCLevel2 6 6.5
OCLevel1,Anyshorttosupply,ground,orotherchannels 7
ISD Overcurrentshutdown A
OCLevel2,Anyshorttosupply,ground,orotherchannels 9
MUTEMODE
GMUTE Outputattenuation 100 dB
CLICKANDPOP
VCP Outputclickandpopvoltage ITU-R2kfilter,High-Z/MUTEtoPlay,PlaytoMute/High-Z 7 mV
DCOFSET
VOFFSET Outputoffsetvoltage 2 5 mV
DCDETECT
DCFAULT OutputDCfaultprotection 2 2.5 V
DIGITALOUTPUTPINS
VOH Outputvoltageforlogiclevelhigh I=±2mA 90 %VDD
VOL Outputvoltageforlogiclevellow I=±2mA 10 %VDD
tDELAY_CLIPD Signaldelaywhenoutputclippingdetected 20 μs
ET
LOADDIAGNOSTICS
Maximumresistancetodetectashortfrom
S2P 500 Ω
OUTpinstoPVDD
Maximumresistancetodetectashortfrom
S2G 200 Ω
OUTpinstoground
SL Shortedloaddetectiontolerance OtherchannelsinHi-Z ±0.5 Ω
OL Openload OtherchannelsinHi-Z 40 70 Ω
TDC_DIAG DCdiagnostictime All4Channels 230 ms
LO Lineoutput 6 kΩ
TLINE_DIAG Lineoutputdiagnostictime 40 ms
Gainlinearity,ƒ=19kHz,RL=2Ωto16Ω, 25%
ACIMP ACimpedanceaccuracy
Offset ±0.5 Ω
TAC_DIAG ACdiagnostictime All4Channels 520 ms
I2C_ADDRPINS
tI2C_ADDR TimedelayneededforI2Caddressset-up 300 μs
(1) TestedwithOutputInductorDFEG7030D-3R3M.
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7.6 Timing Requirements
Testconditions(unlessotherwisenoted):T =25°C,PVDD=VBAT=14.4V,VDD=3.3V,R =4Ω,P =1W/ch,ƒ=1
C L O
kHz,f =2.11MHz,AES17Filter,defaultI2Csettings,seeFigure79andFigure82
SW
MIN TYP MAX UNIT
I2CCONTROLPORT(SeeFigure42)
tBUS Busfreetimebetweenstartandstopconditions 1.3 μs
tHOLD1 Holdtime,SCLtoSDA 0 ns
tHOLD2 Holdtime,startconditiontoSCL 0.6 μs
tSTART I2CstartuptimeafterVDDpoweronreset 12 ms
tRISE Risetime,SCLandSDA 300 ns
tFALL Falltime,SCLandSDA 300 ns
tSU1 Setup,SDAtoSCL 100 ns
tSU2 Setup,SCLtostartcondition 0.6 μs
tSU3 Setup,SCLtostopcondition 0.6 μs
tW(H) RequiredpulsedurationSCLHigh 0.6 μs
tW(L) RequiredpulsedurationSCLLow 1.3 μs
SERIALAUDIOPORT(SeeFigure36)
DMCLK, Allowableinputclockdutycycle 45% 50% 55%
DSCLK
ƒMCLK SupportedMCLKfrequencies:128,256,or512 128 512 xFS
ƒMCLK_Max Maximumfrequency 25 MHz
tSCY SCLKpulsecycletime 40 ns
tSCL SCLKpulse-withLOW 16 ns
tSCH SCLKpulse-withHIGH 16 ns
trise/fall Riseandfalltime 4 ns
tSF SCLKrisingedgetoFSYNCedge 8 ns
tFS FSYNCrisingedgetoSCLKedge 8 ns
tDS DATAset-uptime 8 ns
tDH DATAholdtime 8 ns
ci Inputcapacitance,pinsMCLK,SCLK,FSYNC,SDIN1,SDIN2 10 pF
LatencyfrominputtooutputmeasuredinFSYNC FSYNC=44.1kHzor48kHz 30
TLA samplecount FSYNC=96kHz 12
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