TAS2552 4-W Class-D Mono Audio Amp with Class-G Boost And Speaker Sense datasheet

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TAS2552
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TAS2552 4.0-W Class-D Mono Audio Amplifier with Class-G Boost and Speaker Sense
1 Features 3 Description
• AnalogorDigitalInputMonoBoostedClass-D The TAS2552 is a high efficiency Class-D audio
1 power amplifier with advanced battery current
Amplifier
management and an integrated Class-G boost
• 4.0Winto8 Ω Loadfrom4.2 VSupply(1%
converter. The device constantly measures the
THD+N) current and voltage across the load and provides a
• Efficiencyof 85%atRatedPower digitalstreamofthisinformation.
• I2S,Left-Justified,Right-Justified,DSP,PDM,and The Class-G boost converter generates the Class-D
TDM InputandOutputInterface amplifier supply rail. During low Class-D output
• InputSample Ratesfrom8kHzto192kHz power, the boost improves efficiency by deactivating
andconnectingVBATdirectlytotheClass-Damplifier
• HighEfficiencyClass-GBoostConverter
supply. When high power audio is required, the boost
– AutomaticallyAdjustsClass-D Supply quickly activates to provide significantly louder audio
• Built-InSpeakerSense than a stand-alone amplifier connected directly to the
battery.
– MeasuresSpeakerCurrentandVoltage
– MeasuresVBATandVBOOST Voltages The AGC automatically adjusts Class-D gain to
reduce battery current at end-of-charge voltages,
• Built-InAutomaticGainControl(AGC)
preventingoutput clipping, distortionandearlysystem
– LimitsBatteryCurrentConsumption shutdown. The fixed gain is adjustable via I2C. The
• AdjustableClass-DSwitchingEdge-RateControl gainrangeis-7dBto+24dBin1dBsteps.
• PowerSupplies In addition to a differential mono analog input, the
– BoostInput:3.0Vto5.5V TAS2552hasbuilt-ina16-bitD/Aconverterusedwith
a digital input. Moving the D/A converter from the
– Analog:1.65Vto1.95V
digital host processor into the integrated amplifier
– DigitalI/O:1.5Vto3.6V
process provides better dynamic performance at
• ThermalandShort-CircuitProtection lowersystemcost. Additionally,sincethePCBrouting
• I2CInterfaceforRegisterControl is digital rather than analog, sensitivity to external
perturbations such as GSM frame-rate noise is
• StereoConfigurationUsingTwoTAS2552s
decreasedatthesystemlevel.
– I2CAddressSelectTerminal(ADDR)
• 2.855mmx2.575mm,0.4mmPitch30-Ball
DeviceInformation
WCSP
ORDERNUMBER PACKAGE BODYSIZE
2 Applications TAS2552YFF WCSP(30) 2.855mmx2.575mm
• MobilePhones 2.2 uH
• PND
VBAT 2SW
• PortableAudioDocks 10 nF
VREG
• Tablets +
Audio
• GamingDevices Input - VBOOST
22 uF
PVDD
PDM CLK
TAS2552
Ferrite bead
MCLK
(opt.)
OUT+ +
I2S To
OUT- - Speaker
4
Ferrite bead
I2C (opt.)
VSENSE+
3
Enable VSENSE-
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.
TAS2552
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Table of Contents
1 Features.................................................................. 1 7.5 RegisterMap...........................................................31
2 Applications........................................................... 1 8 ApplicationsandImplementation...................... 42
3 Description............................................................. 1 8.1 ApplicationInformation............................................42
4 RevisionHistory..................................................... 2 8.2 TypicalApplications................................................42
8.3 Initialization.............................................................48
5 PinConfigurationandFunctions......................... 3
9 PowerSupplyRecommendations...................... 49
6 Specifications......................................................... 4
9.1 PowerSupplies.......................................................49
6.1 AbsoluteMaximumRatings......................................4
9.2 PowerSupplySequencing......................................49
6.2 HandlingRatings.......................................................4
9.3 BoostSupplyDetails...............................................50
6.3 RecommendedOperatingConditions.......................4
10 Layout................................................................... 51
6.4 ThermalInformation..................................................4
6.5 ElectricalCharacteristics...........................................5 10.1 LayoutGuidelines.................................................51
6.6 TimingRequirements/TimingDiagrams....................8 10.2 LayoutExample....................................................51
6.7 TypicalCharacteristics..............................................9 10.3 PackageDimensions............................................52
7 DetailedDescription............................................ 13 11 DeviceandDocumentationSupport................. 53
7.1 Overview.................................................................13 11.1 Trademarks...........................................................53
7.2 FunctionalBlockDiagram.......................................13 11.2 ElectrostaticDischargeCaution............................53
7.3 FeatureDescription.................................................14 11.3 Glossary................................................................53
7.4 DeviceFunctionalModes........................................20 12 Mechanical,Packaging,andOrderable
Information........................................................... 54
4 Revision History
ChangesfromRevisionA(February2014)toRevisionB Page
• AddedclarificationonENPinFunctionandConfiguration..................................................................................................... 3
• ChangedVBATMAX=2.45V.AddedfootnotetoavoidVBATreset................................................................................... 7
• AddedclarificationonwaittimeregardingDEV_RESETRegister....................................................................................... 32
• AddedclarificationonVBATresetrangefornormaloperationmode.................................................................................. 49
ChangesfromOriginal(January2014)toRevisionA Page
• ChangedfromProductPreviewtoProductionData.............................................................................................................. 1
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5 Pin Configuration and Functions
30-BallWCSP
YFFPackage
(TopView)
F5 F4 F3 F2 F1
MCLK BCLK WCLK EN IOVDD
E5 E4 E3 E2 E1
SCL IVCLKIN DOUT AIN+ AVDD
D5 D4 D3 D2 D1
SDA ADDR DIN AIN- VBAT
C5 C4 C3 C2 C1
PGND PGND VREG AGND AGND
B5 B4 B3 B2 B1
SW SW VSENSE+ VSENSE- BIAS
A5 A4 A3 A2 A1
VBOOST PVDD OUT+ OUT- PGND
PinFunctions
TERMINAL INPUT/OUTPUT/
DESCRIPTION
NAME BALLWCSP POWER
PGND A1 P Powerground.Connecttohighcurrentgroundplane.
OUT– A2 O InvertingClassDoutput.
OUT+ A3 O Non-invertingClassDoutput.
PVDD A4 P Class-Dpowersupply.ConnectedinternallytoVBOOST–donotdrivethisterminal
externally.
VBOOST A5 P 8.5Vboostoutput.ConnectedinternallytoPVDD–donotdrivethisterminal
externally.
BIAS B1 O Mid-railreferenceforClassDchannel.
VSENSE– B2 I Invertingvoltagesenseinput.
VSENSE+ B3 I Non-invertingvoltagesenseinput.
SW B4,B5 I/O Boostswitchterminal.
AGND C1,C2 P Analogground.Connecttolownoisegroundplane.
VREG C3 O High-sideFETgatedriveboostconverter.
PGND C4,C5 P Powerground.Connecttohighcurrentgroundplane.
VBAT D1 P Batterypowersupply.Connectto3.0Vto5.5Vbatterysupply.
AIN– D2 I Invertinganaloginput.
DIN D3 I Audioserialdatainput.FormatisI2S,LJF,RJF,orTDMdata.
I2Caddressselectterminal.SetADDR=GNDfordevice7-bitaddress0x40;set
ADDR D4 I
ADDR=IOVDDfor7-bitaddress0x41.
SDA D5 I/O I2Ccontrolbusdata.
AVDD E1 P Analoglowvoltagesupplyterminal.Connectto1.65Vto1.95Vsupply.
AIN+ E2 I Non-invertinganaloginput.
DOUT E3 O SerialI/Vdigitaloutput.FormatisI2S,LJF,RJF,TDM,orundecimatedPDMdata.
IVCLKIN E4 I SerialclockinputforundecimatedPDMI/Vdata.
SCL E5 I I2Ccontrolbusclock.
EN(1) F2 I Deviceenable(HIGH=NormalOperation,LOW=Standby)
(1) Waitaminimumof1msafterENispulledhighorDEV_RESETisissuedbeforeaccessingthecontrolinterface.EN=lowwillerasethe
TAS2552deviceconfiguration.TheTAS2552devicemustbeconfigured(seeInitialization)afterEN=high.
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PinFunctions (continued)
TERMINAL INPUT/OUTPUT/
DESCRIPTION
NAME BALLWCSP POWER
WCLK F3 I Audioserialwordclock.
BCLK F4 I Audioserialbitclock.
MCLK F5 I Externalmasterclock.
IOVDD F1 P Supplyfordigitalinputandoutputlevels.Voltagerangeis1.5Vto3.6V.
6 Specifications
6.1 Absolute Maximum Ratings
overoperatingfree-airtemperaturerange,T =25°C(unlessotherwisenoted)
A
MIN MAX UNIT
VBAT Batteryvoltage –0.3 6.0 V
AVDD Analogsupplyvoltage –0.3 2.5 V
IOVDD I/OSupplyvoltage –0.3 3.9 V
AIN+,AIN– Analoginputvoltage –0.3 AVDD+0.3 V
Digitalinputvoltage –0.3 IOVDD+0.3 V
Outputcontinuoustotalpowerdissipation SeeThermalInformation NA
6.2 Handling Ratings
PARAMETER DEFINITION MIN MAX UNIT
T Storagetemperaturerange –65 150 °C
stg
HBM 3000
ESD V
CDM 1500
6.3 Recommended Operating Conditions
overoperatingfree-airtemperaturerange(unlessotherwisenoted)
MIN NOM MAX UNIT
VBAT Batteryvoltage 3.0 5.5 V
AVDD Analogsupplyvoltage 1.65 1.8 1.95 V
IOVDD I/Osupplyvoltage 1.5 1.8 3.6 V
T Operatingfree-airtemperature –40 85 °C
A
T Operatingjunctiontemperature –40 150 °C
J
6.4 Thermal Information
TAS2552
THERMALMETRIC(1) UNIT
YFF(30TERMINALS)
θ Junction-to-ambientthermalresistance 76.5
JA
θ Junction-to-case(top)thermalresistance 0.2
JCtop
θ Junction-to-boardthermalresistance 44.0 °C/W
JB
ψ Junction-to-topcharacterizationparameter 1.6
JT
ψ Junction-to-boardcharacterizationparameter 43.4
JB
(1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication
report,SPRA953.
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6.5 Electrical Characteristics
VBAT=3.6V,AVDD=IOVDD=1.8V,EN=IOVDD,SWS=0,Gain=15dB,ERC=14ns,R =8Ω+33µH,48kHz
L
sampleratefordigitalinput,ILIM=2.5A(unlessotherwisenoted)
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
BOOSTCONVERTER
Averagevoltage(w/oincludingripple).
BoostOutputVoltage Includesloadregulation(0-0.6A)andline 8.5 V
regulation(VBAT=3.0–4.8V).
BoostConverterSwitchingFrequency 1.8 MHz
CLASS-DCHANNEL
MaxAnalogInput ForTHD+N<1% 1 V
RMS
Full-ScaleDACOutput Alldigitalinterfacemodes 1 V
RMS
LoadResistance(LoadSpec
6 8 Ω
Reisistance)
Class-DFrequency 758 kHz
Class-D+BoostEfficiency VBAT=5.5,Pout=1W(sinewave) 75%
Class-DOutputCurrentLimit(Short VBOOST=8.5V,OUT–shortedtoVBAT
3.6 A
CircuitProtection) orVBOOST
VBAT=3.6V,AV=15dB,RL=8Ω,
Class-DOutputOffsetVoltagein
inputshortedtogroundthroughsingle -7.4 4.6 mV
AnalogInputMode
capacitor
Class-DOutputOffsetVoltagein VBAT=3.6V,AV=15dB,RL=8Ω,0's
-9.8 5.6 mV
DigitalInputMode data
ProgrammableChannelGainRange
Typicalvalue,analoganddigitalinput -7 dB
(PGA+class-D),minimum
ProgrammableChannelGainRange
Typicalvalue,analoganddigitalinput 24 dB
(PGA+class-D),maximum
ProgrammableChannelGainStep
Typicalvalue,analoganddigitalinput 1 dB
(PGA+class-D)
MuteAttenuation Deviceinshutdown,digitalinputonly 110 dB
Rippleof200mVpp@217Hz,Gain=15
73
dB,analoganddigitalinput
VBATPowerSupplyRejectionRatio Rippleof200mVpp@1kHz,Gain=15
72 dB
(PSRR) dB,analoganddigitalinput
Rippleof200mVpp@4kHz,Gain=15
72
dB,analoganddigitalinput
Rippleof200mVpp@217Hz,Gain=15
77
dB,analoganddigitalinput
AVDDPowerSupplyRejectionRatio Rippleof200mVpp@1kHz,Gain=15
78 dB
(PSRR) dB,analoganddigitalinput
Rippleof200mVpp@4kHz,Gain=15
84
dB,analoganddigitalinput
Rippleof200mVpp@217Hz,Gain=15
CommonModeRejectionRatio 59 dB
dB,analoginput
1kHz,Po=0.1W,VBAT=3.6V,
0.1%
RL=8Ω
1kHz,Po=0.5W,VBAT=3.6V,
THD+N RL=8Ω 0.1%
1kHz,Po=1W,VBAT=3.6V,RL=8Ω 0.1%
1kHz,Po=2W,VBAT=3.6V,RL=8Ω 0.1%
A-wtFilter,Gain=15dB,DACmodulator
114%
OutputIntegratedNoise(20Hz-20kHz) switching
µV
-8Ω A-wtFilter,Gain=15dB,AnalogIn,
114%
Inputsshorted
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Electrical Characteristics (continued)
VBAT=3.6V,AVDD=IOVDD=1.8V,EN=IOVDD,SWS=0,Gain=15dB,ERC=14ns,R =8Ω+33µH,48kHz
L
sampleratefordigitalinput,ILIM=2.5A(unlessotherwisenoted)
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
THD+N=1%,VBAT=3.0V,ILIM=2.5A 2.8
THD+N=1%,VBAT=3.6V,ILIM=2.5A 3.3
MaxOutputPower,8-ΩLoad W
THD+N=1%,VBAT=4.2V,GAIN=16
4.0
dB,ILIM=3.0A
OutputImpedanceinShutdown EN=0V 10 kΩ
Analog/digitalinputmeasuredfromtime
StartupTime whendeviceistakenoutofsoftware 8 mS
shutdown
Measuredfromtimewhendeviceis
ShutdownTime 1 µS
programmedinsoftwareshutdownmode
INPUTSECTION
Full-scaleDACoutput Alldigitalinterfacemodes 1.0 V
RMS
Maximumanaloginputvoltage 1.0 V
RMS
Inputimpedance(terminalsAIN+, EN=IOVDD,Amplifieractive 10
R kΩ
IN AIN-) EN=0V,Inshutdown 19
CURRENTSENSE
Peakcurrentwhichwillgivefullscale
CurrentSenseFullScale 1.4 A
digitaloutput PEAK
CurrentSenseAccuracy I =354mA (1W) 1%
OUT RMS
CurrentSenseOffset Inputreferred 0.002 mA
CurrentSenseGainError -0.09 dB
THD+N Distortion+Noise Po=1.0W(Load=8Ω+33µH) 0.17%
VOLTAGESENSE
Peakvoltagewhichwillgivefullscale
VoltageSenseFullScale 8.5 V
digitaloutput PEAK
VoltageSenseAccuracy V =2.83Vrms(1W) 2.2%
OUT
VoltageSenseOffset Inputreferred 1.45 mV
VoltageSenseGainError -0.20 dB
THD+N Distortion+Noise Po=1.0W(Load=8Ω+33μH) 0.08%
INTERFACE
F MCLKfrequency 0.512 49.15 MHz
MCLK
F PDMClock(IVCLK)FrequencyRange 1.636 3.25 MHz
PDM
PDMClock(IVCLK)DutyCycle
PDM 40% 60%
DC Range
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Electrical Characteristics (continued)
VBAT=3.6V,AVDD=IOVDD=1.8V,EN=IOVDD,SWS=0,Gain=15dB,ERC=14ns,R =8Ω+33µH,48kHz
L
sampleratefordigitalinput,ILIM=2.5A(unlessotherwisenoted)
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
POWERCONSUMPTION
FromVBAT,PLLoff,nosignal 6.54 mA
PowerConsumptionwithAnalogInput
FromAVDD,PLLoff,nosignal 4.01 mA
andIVSenseDisabled
FromIOVDD,PLLoff,nosignal 0.04 mA
FromVBAT,PLLoff,nosignal 6.82 mA
PowerConsumptionwithDigitalInput
FromAVDD,PLLoff,nosignal 4.16 mA
andIVSenseDisabled
FromIOVDD,PLLoff,nosignal 0.34 mA
FromVBAT,PLLon,nosignal 6.54 mA
PowerConsumptionwithAnalogInput
FromAVDD,PLLon,nosignal 7.26 mA
andIVSenseEnabled
FromIOVDD,PLLon,nosignal 0.05 mA
FromVBAT,PLLon,nosignal 6.59 mA
PowerConsumptionwithDigitalInput
FromAVDD,PLLon,nosignal 8.34 mA
andIVSenseEnabled
FromIOVDD,PLLon,nosignal 0.34 mA
FromVBAT,EN=0 0.1 µA
PowerConsumptioninHardware
FromAVDD,EN=0 0.2 µA
Shutdown
FromIOVDD,EN=0 0.0 µA
FromVBAT 6.5 µA
PowerConsumptioninSoftware
FromAVDD 8.6 µA
Shutdown
FromIOVDD 126 µA
DIGITALINPUT/OUTPUT
0.7x
V High-leveldigitalinputvoltage V
IH IOVDD
0.3x
V Low-leveldigitalinputvoltage V
IL IOVDD
0.9x
V High-leveldigitaloutputvoltage V
OH IOVDD
0.1x
V Low-leveldigitaloutputvoltage V
OL IOVDD
MISCELLANEOUS
AVDDSupplyUnder-voltage Deviceisinresetstate 0.9
V
Threshold Devicecomesoutofresetstate 1.4
VBATSupplyUnder-voltage Deviceisinresetstate 1.8
V
Threshold Devicecomesoutofresetstate 2.45(1)
(1) VBATmustbe≥2.45Vtoguaranteethatthedeviceisnotreset.
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6.6 Timing Requirements/Timing Diagrams
ForI2Cinterfacesignalsoverrecommendedoperatingconditions(unlessotherwisenoted).Note:Alltimingspecificationsare
measuredatcharacterizationbutnottestedatfinaltest.
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
f Frequency,SCL Nowaitstates 400 kHz
SCL
t Pulseduration,SCLhigh 0.6 µs
W(H)
t Pulseduration,SCLlow 1.3 µs
W(L)
t Setuptime,SDAtoSCL 100 ns
su1
t Holdtime,SCLtoSDA 10 ns
h1
Busfreetimebetweenstopandstart
t 1.3 µs
(buf) condition
t Setuptime,SCLtostartcondition 0.6 µs
su2
t Holdtime,startconditiontoSCL 0.6 µs
h2
t Setuptime,SCLtostopcondition 0.6 µs
su3
tw(H) tw(L)
SCL
t th1
su1
SDA
Figure1. SCLandSDATiming
SCL
th2 t(buf)
tsu2 tsu3
SDA
Start Condition Stop Condition
Figure2. StartandStopConditionsTiming
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6.7 Typical Characteristics
VBAT=3.6V,AVDD=IOVDD=1.8V,EN=IOVDD,SWS=0,R =8Ω+33µH(unlessotherwisenoted).
L
100 100
VBAT = 3.0 V VBAT = 3.0 V
VBAT = 3.6 V VBAT = 3.6 V
10 VBAT = 4.2 V 10 VBAT = 4.2 V
% VBAT = 5.0 V % VBAT = 5.0 V
+N - 1 VBAT = 5.5 V +N - 1 VBAT = 5.5 V
D D
H H
T T
0.1 0.1
0.01 0.01
0.0001 0.001 0.01 0.1 1 0.001 0.01 0.1 1
P - Output Power - W P - Output Power - W
O C004 O C024
AGC=OFF,Gain=15dB AGC=OFF,Gain=15dB
Figure3.THD+NvsOutputPower(8Ω)forDigitalInput Figure4.THD+NvsOutputPower(6Ω)forDigitalInput
1 100
VBAT = 5.5 V
VBAT = 5.0 V
10 VBAT = 4.2 V
0.1
% % VBAT = 3.6 V
+N - + N - 1 VBAT = 3.0 V
THD 0.01 VBAT = 5.5 V THD
VBAT = 5.0 V
0.1
VBAT = 4.2 V
VBAT = 3.6 V
VBAT = 3.0 V
0.001 0.01
20 200 2000 20000 0.001 0.01 0.1 1
f - Frequency - Hz C005 PO - Output Power - W C006
AGC=OFF,Gain=15dB,Pout=1W AGC=OFF,Gain=15dB,f=1kHz
Figure5.THD+NvsFrequency(8Ω)forDigitalInput Figure6.THD+NvsOutputPower(8Ω)forAnalogInput
1 4.0
3.5
W 3.0
% 0.1 er - 2.5
N - Pow
D + VBAT = 5.5 V put 2.0
TH 0.01 VVBBAATT == 54..02 VV P - OutO11..05
VBAT = 3.6 V 0.5 THD + N = 1%
VBAT = 3.0 V THD + N = 10%
0.001 0.0
20 200 2000 20000 2.5 3 3.5 4 4.5 5 5.5
f - Frequency - Hz V - Supply Voltage - V
C007 BAT C008
AGC=OFF,Gain=15dB AGC=OFF,Gain=24dB,f=1kHz
Figure7.THD+NvsFrequency(8Ω)forAnalogInput Figure8.OutputPowerfor1%and10%THD+NvsSupply
Voltage(8Ω)
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Typical Characteristics (continued)
VBAT=3.6V,AVDD=IOVDD=1.8V,EN=IOVDD,SWS=0,R =8Ω+33µH(unlessotherwisenoted).
L
10.000 100
APT Transition
1.000 80
A
nt -
Curre 0.100 ency 60
y ci VBAT = 5.5 V
ppl 0.010 VBAT = 5.5 V Effi 40
u VBAT = 5.0 V
S VBAT = 5.0 V
I - DD 0.001 VBAT = 4.2 V 20 VBAT = 4.2 V
VBAT = 3.6 V VBAT = 3.6 V
VBAT = 3.0 V VBAT = 3.0 V
0.000 0
0.010 0.100 1.000 0.01 0.1 1
PO - Total Output Power - W C009 PO - Total Output Power - W C010
AGC=OFF,Gain=15dB,f=1kHz AGC=OFF,Gain=15dB,f=1kHz
Figure9.VBATAverageSupplyCurrentvsClass-DOutput Figure10.TotalEfficiencyvsOutputPower(8Ω)
Power(8Ω)
0.010 0
B VBAT = 5.5 V
d
0.008 atio - ±20 VVBBAATT == 54..02 VV
A R
urrent - 0.006 ejection ±40 VVBBAATT == 33..60 VV
C R
upply 0.004 Mode ±60
S n
0.002 mo ±80
m
o
C

0.000 ±100
3.0 3.5 4.0 4.5 5.0 5.5 20 200 2000 20000
V - Supply Voltage - V f - Frequency - Hz
BAT C011 C012
VBAT=3.0,3.6,4.2,5.0,5.5V 20Hzto20kHz,AnalogInput,Gain=15dB
Figure11.VBATQuiescentSupplyCurrentvsSupply Figure12.CommonModeRejectionvsFrequency
Voltage
0 0
VBAT = 5.5 V AVDD = 1.8 V
VBAT = 5.0 V
VBAT = 4.2 V -20
±20 VBAT = 3.6 V
VBAT = 3.0 V
B B -40
d d
R - ±40 R -
R R
S S -60
P P
±60
-80
±80 -100
20 200 2000 20000 20 200 2000 20000
f - Frequency - Hz C013 f - Frequency - Hz C014
20Hzto20kHz,DigitalInput,Gain=15dB 20Hzto20kHz,DigitalInput,Gain=15dB
Figure13.VBATSupplyRippleRejectionvsFrequency Figure14.AVDDSupplyRippleRejectionvsFrequency
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