Smart and flexible digital-to-analog converters

325 Pages·2011·17.87 MB·English

by  Georgi Radulov

Analog Circuits and Signal Processing
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http://www.springer.com/series/7381
Georgi Radulov • Patrick Quinn
Hans Hegt • Arthur van Roermund
Smart and Flexible
Digital-to-Analog Converters
1  3
Dr. eng. Georgi Radulov, PDEng Dr. ir. Hans Hegt
Department of Electrical Engineering Department of Electrical Engineering
Eindhoven University of Technology Eindhoven University of Technology
Den Dolech 2, Eindhoven, Den Dolech 2, Eindhoven,
5612 AZ 5612 AZ
The Netherlands The Netherlands
[email protected] [email protected]
Dr. M.Sc. Patrick Quinn Prof. dr. ir. Arthur van Roermund
Xilinx Department of Electrical Engineering
Analog Mixed Signal Design Group Eindhoven University of Technology
Citywest Business Campus, Saggart Den Dolech 2, Eindhoven,
One Logic Dr., Dublin, Ireland 5612 AZ
[email protected] The Netherlands
[email protected]
ISBN 978-94-007-0346-9
DOI 10.1007/978-94-007-0347-6
Springer Dordrecht Heidelberg London New York
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Abstract
This research work proposes new concepts of flexibility and self-correction for
current-steering digital-to-analog converters (DACs) which allow the attainment of
broad functional and performance specifications, high linearity, and reduced depen-
dence on the fabrication processes.
This work analytically investigates the DAC linearity with respect to the ac-
curacy of the DAC unit elements. The main novelty of the proposed approach is
in the application of the Brownian Bridge (BB) process to precisely describe the
DAC Integrated-Non-Linearity (INL). The achieved results fill a gap in the general
understanding of the most quoted DAC specification—the INL.
Further, this work introduces a classification of the highly diverse current-steer-
ing DAC correction methods. The classification automatically points to methods
that do not exist yet in the open literature (gaps). Based on the clues of the common
properties and identified common techniques in the introduced classification, this
work then proposes exemplary solutions to fill in the identified gaps.
Further, this work systematically analyses self-calibration correction methods
for the DAC mismatch errors. Their components are analyzed as three building
blocks: self-measurement, error processing algorithm and self-correction block.
This work systemizes their alternative implementations and the associated trade-
offs. The findings are compared to the available solutions in the literature. The ef-
ficient calibration of the DAC binary currents is identified as an important missing
method. This work proposes a new methodology for correcting the mismatch errors
of both the nominally identical unary and the scaled binary DAC currents.
Further, this work proposes a new concept for DAC flexibility. This concept is
realized in a new flexible DAC architecture. The architecture is based on a modular
design approach that uses parallel sub-DAC units to realize flexible design, flexible
functionality and flexible performance. The parallel sub-DAC units form a mixed-
signal platform that is capable of many DAC correction methods, including calibra-
tion, error mapping, data reshuffling, and harmonic distortion cancellation.
This work presents the implementation and measurement results of three DAC
test-chip implementations in 250 nm, 180 nm, and 40 nm standard CMOS IC
technologies. The test-chips are used as a tool to practically investigate, validate,
and demonstrate two main concepts of this book: self-calibration and flexibility.
v
vi Abstract
Particularly, the 180 nm test-chip is the first reported DAC implementation that
calibrates the errors of all its current sources and features flexibility, as suggested
in this work. The calibration of all current sources makes the DAC accuracy inde-
pendent of the tolerances of the manufacturing process. The overall DAC accuracy
depends on a single design parameter—the correction step. The third test-chip is the
first reported DAC implementation in 40 nm CMOS process. A 12 bit DAC core in
this test-chip occupies only 0.05 mm2 of silicon area, which is the smallest reported
area for a 12 bit current-steering DAC core.
Contents
Part I Introduction and Basics ................................................................... 1
1 Introduction ............................................................................................... 3
1.1 Modern Micro-electronics and Flexibility ......................................... 3
1.2 Aims of the Book ............................................................................... 5
1.3 Scope of the Book .............................................................................. 6
1.4 Scientific Approach ............................................................................ 6
1.5 Outline of the Book ............................................................................ 7
2 Basics of Digital-to-Analog Conversion .................................................. 11
2.1 Introduction ........................................................................................ 11
2.2 Functionality and Specifications ........................................................ 12
2.2.1 Static Characterization ........................................................... 12
2.2.2 Dynamic Characterization ..................................................... 15
2.3 DAC Resources .................................................................................. 16
2.4 Segmentation of DAC Analog Resources .......................................... 18
2.4.1 Binary Algorithmic Segmentation ......................................... 19
2.4.2 Sub-binary Radix Algorithmic Segmentation ........................ 20
2.4.3 Unary Algorithmic Segmentation .......................................... 21
2.4.4 Binary LSB and Unary MSB Algorithmic Segmentation ...... 22
2.5 DAC Implementations ....................................................................... 23
2.6 Current-Steering DAC Architecture .................................................. 25
2.7 Modern Current-Steering DAC Challenges ....................................... 26
2.8 Summary ............................................................................................ 29
Part II State-of-the-Art Correction Methods ............................................. 31
3 Error Correction by Design ..................................................................... 33
3.1 Introduction ........................................................................................ 33
3.2 Return-to-Zero Output ....................................................................... 34
3.3 Differential-Quad Switching .............................................................. 36
3.4 Cascode Switches with Offset Current .............................................. 37
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vviiiiii Contents
3.5 Input Data Reshuffling Methods (DEM) ........................................... 38
3.6 Discussion .......................................................................................... 41
3.7 Conclusions ........................................................................................ 41
4 Smart Self-Correcting D/A Converters ................................................... 43
4.1 Introduction ........................................................................................ 43
4.2 Self-Calibration of DAC Current Cells .............................................. 44
4.2.1 A mplitude Errors Self-Calibration ......................................... 45
4.2.2 T iming Errors Self-Calibration .............................................. 46
4.2.3 Discussion .............................................................................. 47
4.3 Mapping ............................................................................................. 47
4.3.1 Low Level Maps for DAC Unary Current Cells .................... 48
4.3.2 Low-Level Maps for Sub-binary Radix DACs ...................... 51
4.4 Digital Pre-distortion ......................................................................... 53
4.5 Discussion .......................................................................................... 54
4.6 Conclusions ........................................................................................ 55
Part III New Modeling, Analysis, and Classification ................................ 57
5 Error Modeling for DAC Correction, a Broad View ............................. 59
5.1 Introduction ........................................................................................ 59
5.2 A Model of the Step Response of a Current Cell ............................... 61
5.3 Transistor Mismatch Caused Errors ................................................... 62
5.4 Digital-Switching Errors .................................................................... 66
5.5 Discussion .......................................................................................... 68
5.6 Conclusions ........................................................................................ 70
6 Brownian Bridge Based Analysis and Modeling of DAC
Linearity, an In-depth View ..................................................................... 71
6.1 Introduction ........................................................................................ 71
6.2 New Statistical Analysis of the DAC Static Non-linearity
Based on Brownian Bridge ................................................................ 73
6.2.1 Unary DAC ............................................................................ 74
6.2.2 Binary DAC ........................................................................... 78
6.3 Discussion .......................................................................................... 81
6.4 Conclusions ........................................................................................ 83
7 Classification of Error Correction Methods, a Broad View .................. 85
7.1 Introduction ........................................................................................ 85
7.2 Selected Set of DAC Correction Methods and Definitions ............... 86
7.3 Error Measurement Category ............................................................. 88
7.4 Redundancy Category ........................................................................ 91
7.5 System Level Category ...................................................................... 92
7.6 Discussion .......................................................................................... 93
7.7 Conclusion ......................................................................................... 94
Contents iixx
8 Analysis of Self-Calibration of Currents, an In-depth View ............... 95
8.1 Introduction ...................................................................................... 95
8.2 DAC Currents Self-Calibration Classification ................................. 96
8.3 Self-Measurement ............................................................................ 98
8.3.1 Measurement Probes ............................................................ 98
8.3.2 Reference ............................................................................. 104
8.3.3 Measurement Device ........................................................... 105
8.4 A lgorithm ......................................................................................... 113
8.4.1 Unary-Currents Calibration ................................................. 113
8.4.2 New Binary-Currents Calibration in a Unary Way .............. 116
8.4.3 New True Binary-Currents Calibration ................................ 117
8.5 Self-Correction ................................................................................. 121
8.5.1 Self-Correction Method ....................................................... 121
8.5.2 Correction Circuits ............................................................... 123
8.5.3 Correction Memory .............................................................. 125
8.6 Conclusions ...................................................................................... 126
Part IV New Concepts and Methods ........................................................ 129
9 New Redundant Segmentation Concept ............................................... 131
9.1 Introduction ...................................................................................... 131
9.2 Abstraction Levels of Segmentation ................................................ 134
9.3 New Redundant Segmentation ......................................................... 136
9.4 Discussion ........................................................................................ 139
9.5 Conclusion ....................................................................................... 140
10 New Methods for Self-Calibration of Currents .................................... 141
10.1 Introduction ...................................................................................... 141
10.2 Self-Calibration of Unary Currents .................................................. 142
10.2.1 New Calibration Method ................................................... 142
10.2.2 Conclusions ........................................................................ 148
10.3 A Calibration Method for Generic Current-Steering D/A
Converters with Optimal Area Solution ........................................... 148
10.3.1 New Self-Calibrating Current Cell for a Generic
DAC Architecture .............................................................. 149
10.3.2 Area Driven Optimum of the Level of Calibration ............ 150
10.3.3 Discussion .......................................................................... 152
10.3.4 Conclusions ........................................................................ 153
10.4 A Calibration Method for Binary Signal Current Sources ............... 153
10.4.1 Calibration of Scaled Currents ........................................... 154
10.4.2 Conclusions ........................................................................ 157
10.5 Discussion ........................................................................................ 157
10.6 Conclusions ...................................................................................... 157