Single and Multi-Chip Microcontroller Interfacing : For the Motorola 6812 (Academic Press Series in Engineering)

513 Pages·1999·61.77 MB·English

by  G. Jack Lipovski

Single- and Multi-Chip
Microcontroller Interfacing
For the Motorola 68HC12
Academic Press Series in Engineering
Series Editor
J. David Irwin
Auburn University
Designed to bring together interdependent topics in electrical engineering, mechanical
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Published books in the series:
Industrial Controls and Manufacturing, 1999, E. Kamen
DSP Integrated Circuits, 1999, L. Wanhammar
Time Domain Electromagnetics, 1999, S. M. Rao
Single- and Multi-Chip Microcontroller Interfacing for the Motorola 68HC12, 1999,
G. J. Lipovski
Control in Robotics and Automation, 1999, B. K. Ghosh, N. Xi, T. J. Tarn
Single- and Multi-Chip
Microcontroller Interfacing
For the Motorola 68HC12
G. Jack Lipovski
Department of Electrical and Computer Engineering
University of Texas
Austin, Texas
ACADEMIC PRESS
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Copyright © 1999 by Academic Press
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Library of Congress Catalog Card Number: 98-89451
ISBN: 0-12-451830-3
Printed in the United States of America
99 00 01 02 03 MV 9 8 7 6 5 4 3 2 1
Disclaimer:
This eBook does not include the ancillary media that was
packaged with the original printed version of the book.
Dedicated to my mother,
Mary Lipovski
About the Author
G. Jack Lipovski has taught electrical engineering and computer science at the
University of Texas since 1976. He is a computer architect internationally recognized for his
design of the pioneering database computer, CASSM, and the parallel computer, TRAC. His
expertise in microcomputers is also internationally recognized by his being a past director of
Euromicro and an editor of IEEE Micro. Dr. Lipovski has published more than 70 papers,
largely in the proceedings of the annual symposium on computer architecture, the IEEE
transactions on computers and the national computer conference. He holds eight patents,
generally in the design of logic-in-memory integrated circuits for database and graphics
geometry processing. He has authored seven books and edited three. He has served as chair-
man of the IEEE Computer Society Technical Committee on Computer Architecture, mem-
ber of the Computer Society Governing Board, and chairman of the Special Interest Group
on Computer Architecture of the Association for Computer Machinery. He has been elected
Fellow of the IEEE and a Golden Core Member of the IEEE Computer Society. He received
his Ph.D. degree from the University of Illinois, 1969, and has taught at the University of
Florida, and at the Naval Postgraduate School, where he held the Grace Hopper chair in
Computer Science. He has consulted for Harris Semiconductor, designing a microcomputer,
and for the Microelectronics and Computer Corporation, studying parallel computers. He
founded the company Linden Technology Ltd., and is the chairman of its board. His current
interests include parallel computing, database computer architectures, artificial intelligence
computer architectures, and microcomputers.
Contents
Preface x i i i
List of Figures xvii
List of Tables xxi
Acknowledgments xxi
About the Author xxiii
I Microcomputer Architecture I
1.1 An Introduction to the Microcomputer I
1.1.1 Computer Architecture 2
1.1.2 The Instruction 6
1.1.3 Microcomputers 9
1.2 The 6812 Instruction Set 11
1.2.1 6812 Addressing Modes 11
1.2.2 6812 Data Operator Instructions 16
1.2.3 6812 Control Instructions 23
1.3 Assembly-Language Directives 28
1.4 Organization of 6812 Microcontrollers 31
1.4.1 Notation for Block Diagrams 31
.,4.2 6812 Microcontroller I/O and Memory Organization 31
1.4.3 The MC68HC812A4 and MC68HC912B32 Memory Maps 35
1.5 Conclusions 36
Problems 38
2 Programming Microcomputers 45
2.1 Introduction to C 46
2.2 Data Structures 55
2.2.1 Indexable Data Structures 57
2.2.2 Sequential Data Structures 59
2.3 Writing Clear C Programs 66
2.3.1 C Procedures and Their Arguments 66
2.3.2 Programming Style 72
2.3.3 Object-Oriented Programming 73
2.3.4 Optimizing C Programs Using Declarations 83
2.3.5 Optimizing C Programs with Assembly Language 83
2.4 Conclusions 84
Problems 86
vu
Contents
3 Bus Hardware and Signals 93
3.1 Digital Hardware 94
3.1.1 Modules and Signals 94
3.1.2 Drivers, Registers, and Memories 97
3.2 Address and Control Signals in 6812 Microcontrollers 104
3.2.1 Address and Control Timing 104
3.2.2 Address and Control Signal Decoding 108
3.3 Conclusions 113
Problems 115
4. Parallel and Serial Input/Output
4.1 I/O Devices and Ports
4.1.1 Generic Port Architecture
4.1.2 Generic Port Classes
4.1.3 Debugging Tools
4.2 6812 Parallel Ports
4.2.1 MC68HC812A4 Port Architecture
4.2.2 MC68HC912B32 Port Architecture
4.2.3 Programming of PORTA
4.2.4 A Class for Ports with Direction Control
4.3 Input/Output Software
4.3.1 A Wire
4.3.2 A Movie
4.3.3 A Traffic Light Controller
4.3.4 A Sequential Machine
4.3.5 An IC Tester
4.3.6 Object-oriented Vector Functions and Interpreters
4.4 Input/Output Indirection
4.4.1 Indirect Input/Output
4.4.2 LCD Interfacing
4.4.3 Synchronous Serial Input/Output
4.4.4 The 6812 SPI Module
4.4.5 Accessing Devices Using Vectors and structs
4.4.5.1 Vector Access to Ports
4.4.5.2 Vector Pointer Access to Ports
4.4.5.3 Using #defines to Name Ports
4.4.5.4 Struct Pointer Access to Ports
4.4.5.5 Struct Access to Ports
4.4.6 Indirect and Serial I/O Objects
4.5 A Designer's Selection of I/O Ports and Software
4.6 Conclusions
Problems
Contents
5 Interrupts and Alternatives 193
5.1 Programmed Synchronization 196
5.1.1 Real-time Synchronization 196
5.1.2 Gadfly Synchronization 198
5.1.2.1 MC68HC812A4 Gadfly Synchronization 199
5.1.2.2 MC68HC912B32 Gadfly Synchronization 200
5.1.2.3 Gadfly Synchronization Characteristics 200
5.1.3 Handshaking 200
5.1.4 Some Examples of Programmed I/O 201
5.1.5 Object-oriented Classes for Programmed I/O 204
5.2 Interrupt Synchronization 210
5.2.1 Steps in an Interrupt 210
5.2.1.1 Steps in an Interrupt in the MC68HC812A4 211
5.2.1.2 Steps in an Interrupt in the MC68HC912B32 212
5.2.1.3 Properties of Interrupt Synchronization 213
5.2.2 Interrupt Handlers and Critical Sections 214
5.2.2.1 A Handler That Changes a Global Variable 214
5.2.2.2 A Handler That Fills or Empties a Buffer 216
5.2.2.3 A Handler That Uses a Queue for Input 218
5.2.2.4 A Handler That Uses a Queue for Output 220
5.2.2.5 Critical Sections 221
5.2.3 Polled Interrupts 222
5.2.3.1 Polled Interrupts in the MC68HC812A4 222
5.2.3.2 Polled Interrupts in the MC68HC912B32 224
5.2.3.3 Service Routines 225
5.2.3.4 Round-robin Handlers 226
5.2.4 Vectored Interrupts 228
5.2.4.1 Vectored Interrupts in the MC68HC812A4 228
5.2.4.2 Vectored Interrupts in the MC68HC912B32 230
5.2.4.3 Vectored Interrupts for Other Devices 231
5.2.5 Examples of Interrupt Synchronization 231
5.2.5.1 Keyboard Handling 23 i
5.2.5.2 Interrupts for SPI Systems 235
5.2.5.3 Histograms and Histories for the MC68HC812A4 236
5.2.6 Object-oriented Classes for Interrupts 237
5.2.6.1 An IQFPort Class 237
5.2.6.2 An OQFPort Class 239
5.2.6.3 Polling IQFPort and OQFPort Classes 240
5.2.6.4 Bar-code Class 240
5.2.6.5 An X-10 Class 241
5.3 Time-Sharing 244
5.3.1 Real-time Interrupts 244
5.3.2 Multithread Scheduling 245
5.3.3 Threads for Time-sharing 248
5.3.4 An Efficient Time Schedular 252
5.3.5 Special Instructions for Time-sharing 256