Practical Microcontroller Engineering with ARM Technology

1020 Pages·2016·51.64 MB·English

by  Ying Bai

Practical Microcontroller
Engineering with

ARM Technology
IEEE Press
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Piscataway, NJ 08854
IEEE Press Editorial Board
Tariq Samad, Editor in Chief
GeorgeW.Arnold VladimirLumelsky LindaShafer
DmitryGoldgof Pui-InMak ZidongWang
EkramHossain JeffreyNanzer MengChuZhou
MaryLanzerotti RayPerez GeorgeZobrist
Kenneth Moore, Director of IEEE Book and Information Services (BIS)
Practical Microcontroller
Engineering with

ARM Technology
Ying Bai
Department ofComputerScience and Engineering
Johnson C.Smith University
Charlotte, North Carolina
Copyright2016byTheInstituteofElectricalandElectronicsEngineers,Inc.
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This book is dedicated to my wife, Yan Wang,
and to my daughter, Susan (Xue) Bai.

Contents
Preface xxix
Acknowledgments xxxi
TrademarksandCopyrights xxxiii
CopyrightPermissions xxxv
AbouttheCompanionWebsite xxxix
Chapter1 IntroductiontoMicrocontrollersandThisBook 1
1.1 MicrocontrollerConfigurationandStructure 2
1.2 TheARM CortexM4MicrocontrollerSystem 3
1.3 TheTM4C123GH6PMMicrocontrollerDevelopmentToolsandKits 4
1.4 OutstandingFeaturesAboutThisBook 5
1.5 WhoThisBookIsFor 5
1.6 WhatThisBookCovers 6
1.7 HowThisBookIsOrganizedandHowtoUseThisBook 8
1.8 HowtoUsetheSourceCodeandSampleProjects 9
1.9 InstructorsandCustomersSupports 11
Chapter2 ARM MicrocontrollerArchitectures 13
2.1 OverviewandIntroduction 13
2.2 IntroductiontoARM Cortex-M4MCU 15
2.2.1 TheArchitectureofARM Cortex-M4MCU 17
2.2.1.1 TheARM MCUArchitecture 17
2.2.1.2 TheArchitectureoftheARM Cortex-M4Core(CPU) 20
2.2.1.2.1 TheRegisterBankintheCortex-M4Core 21
2.2.1.2.2 TheSpecialRegistersintheCortex-M4Core 22
2.2.1.3 TheArchitectureoftheFloating-PointRegisters 25
2.3 TheMemoryArchitecture 27
2.3.1 TheMemoryMap 28
2.3.2 TheStackMemory 29
2.3.3 TheProgramModelsandStates 32
2.3.4 TheMemoryProtectionUnit(MPU) 33
2.4 TheNestedVectoredInterruptController(NVIC)Architecture 34
2.4.1 TheNestedVectoredInterruptController(NVIC)Features 35
2.4.2 ExceptionandInterruptSources 35
2.4.3 ExceptionPriorityLevelsandMaskRegisters 35
vii
viii Contents
2.4.4 RespondandProcessExceptionsandInterrupts 36
2.4.5 ExceptionandInterruptVectorTable 37
2.5 TheDebugArchitecture 37
2.6 IntroductiontoTivaTMCSeriesARM Cortex-M4MCU-TM4C123GH6PM 38
2.6.1 TM4C123GH6PMMicrocontrollerOverview 39
2.6.2 TM4C123GH6PMMicrocontrollerOn-ChipMemoryMap 40
2.6.2.1 TheSystemPeripherals 42
2.6.2.2 TheOn-ChipPeripherals 42
2.6.2.3 InterfacestoExternalParallelPeripherals 44
2.6.2.4 InterfacestoExternalSerialPeripherals 44
2.6.3 TM4C123GH6PMMicrocontrollerGeneral-PurposeInput–Output
(GPIO)Module 44
2.6.3.1 TheSystemClock 45
2.6.3.2 TheGeneralConfigurationProceduresforGPIOPeripherals 47
2.6.3.3 TivaTMTM4C123GH6PMGPIOArchitecture 47
2.6.3.3.1 ThePortControlRegister(GPIOPCTL) 49
2.6.3.3.2 TheDataControlRegisters 49
2.6.3.3.3 TheModeControlRegisters 49
2.6.3.3.4 TheCommitControlRegisters 51
2.6.3.3.5 TheInterruptControlRegisters 51
2.6.3.3.6 ThePadControlRegisters 52
2.6.3.3.7 TheIdentificationRegisters 55
2.6.3.4 TheInitializationandConfigurationofTM4C123GH6PM
GPIOPorts 55
2.6.4 TM4C123GH6PMMicrocontrollerSystemControls 57
2.6.4.1 DeviceIdentification 58
2.6.4.2 ResetControl 59
2.6.4.2.1 ThePower-OnReset 60
2.6.4.2.2 TheExternalReset 61
2.6.4.2.3 TheBrown-OutReset(BOR) 61
2.6.4.2.4 TheSoftwareReset 61
2.6.4.2.5 TheWatchdogTimerReset 62
2.6.4.3 Non-MaskableInterruptControl 63
2.6.4.4 ClockControl 64
2.6.4.5 OtherSystemControls 67
2.6.4.5.1 TheRunMode 67
2.6.4.5.2 TheSleepMode 68
2.6.4.5.3 TheDeep-SleepMode 68
2.6.4.5.4 TheHibernateMode 68
2.6.4.5.5 TheSystemTimer(SysTick) 69
2.6.4.5.6 SystemControlBlock(SCB) 70
2.6.4.6 SystemClockInitializationandConfiguration 71
2.7 IntroductiontoTivaTMCSeriesLaunchPadTMTM4C123GXL
EvaluationBoard 72
2.8 IntroductiontoEduBASEARM Trainer 77
2.9 ChapterSummary 77
Homework 79
Contents ix
Chapter3 ARM MicrocontrollerDevelopmentKits 83
3.1 OverviewandIntroduction 83
3.2 TheEntireTivaTMTM4C123G-basedDevelopmentSystem 84
3.3 DownloadandInstallDevelopmentSuiteandSpecifiedFirmware 86
3.4 IntroductiontotheIntegratedDevelopmentEnvironment—Keil MDK
μVersion5 87
3.4.1 TheKeil MDK-ARM fortheMDK-Cortex-MFamily 88
3.4.2 GeneralDevelopmentFlowwithMDK-ARM 89
3.4.3 WarmingUpKeil MDKCortex-MKitwithExampleProjects 91
3.4.4 TheFunctionsoftheKeil MDK-ARM μVersion5GUI 95
3.4.4.1 TheFileMenu 97
3.4.4.2 TheEditMenu 98
3.4.4.3 TheProjectMenu 101
3.4.4.4 TheFlashMenu 121
3.4.4.5 TheDebugMenu 121
3.4.4.6 ThePeripheralsMenu 123
3.4.4.7 TheToolsMenu 124
3.4.4.8 TheSVCSMenu 125
3.4.4.9 TheWindowMenu 126
3.4.4.10 TheHelpMenu 126
3.5 EmbeddedSoftwareDevelopmentProcedure 127
3.6 TheKeil ARM-MDKμVision5DebuggerandDebugProcess 128
3.6.1 TheARM μVision5DebugArchitecture 129
3.6.2 TheARM DebugAdaptorandDebugAdaptorDriver 130
3.6.3 TivaTMCSeriesLaunchPadTMDebugAdaptorandDebugAdaptorDriver 132
3.6.4 TheARM μVersion5DebugProcess 133
3.6.5 TheARM TraceFeature 134
3.6.5.1 SomeUsefulTraceFeaturesProvidedbyCortex-M4MCU 135
3.6.6 TheARM InstructionSetSimulator 136
3.6.7 TheARM ProgramsRunningfromSRAM 137
3.6.8 ARM Optimizations 139
3.7 TheTivaWareTMforCSeriesSoftwareSuite 140
3.7.1 TheTivaWareTMCSeriesSoftwarePackage 142
3.7.1.1 ThePeripheralDriverLibrary(DriverLib) 143
3.7.1.2 TheBootLoader 144
3.7.1.3 TheUtilities 144
3.7.2 TivaWareTMCSeriesforTM4C123GLaunchPadTMEvaluationKit 145
3.7.2.1 TivaWareTMCSeriesLaunchPadTMEvaluationSoftware
Package 145
3.8 TheTivaWareTMforCSeriesUtilitiesandOtherSupports 147
3.8.1 AdditionalUtilitiesProvidedbyTivaWareTMforCSeries 148
3.8.1.1 TheLMFlashProgrammer 148
3.8.1.2 TheUniFlash 149
3.8.1.3 TheFTDIDrivers 149
3.8.1.4 TheIQMathLibrary 149
3.8.1.5 TivaWareTMforCSeriesCMSISSupport 150
x Contents
3.9 ProgramExamples 151
3.10 ChapterSummary 152
Homework 152
Chapter4 ARM MicrocontrollerSoftwareandInstructionSet 155
4.1 OverviewandIntroduction 155
4.2 IntroductiontoARM Cortex-M4SoftwareDevelopmentStructure 156
4.3 IntroductiontoARM Cortex-M4AssemblyInstructionSet 157
4.3.1 TheARM Cortex-M4AssemblyLanguageSyntax 158
4.3.2 TheARM Cortex-M4PseudoInstructions 160
4.3.3 TheARM Cortex-M4AddressingModes 161
4.3.3.1 TheImmediateOffsetAddressingMode 162
4.3.3.1.1 RegularImmediateOffsetAddressingMode 162
4.3.3.1.2 Pre-IndexedImmediateOffsetAddressingMode 163
4.3.3.1.3 Post-IndexedImmediateOffsetAddressingMode 163
4.3.3.1.4 RegularImmediateOffsetAddressingModewithUnprivileged
Access 163
4.3.3.2 TheRegisterOffsetAddressingMode 164
4.3.3.3 ThePC-RelativeAddressingMode 165
4.3.3.4 LoadandStoreMultipleRegistersAddressingMode 167
4.3.3.5 PUSHandPOPRegisterAddressingMode 170
4.3.3.6 LoadandStoreRegisterExclusiveAddressingMode 170
4.3.3.7 InherentAddressingMode 171
4.3.3.8 AddressingModeSummary 171
4.3.4 TheARM Cortex-M4InstructionSetCategories 172
4.3.4.1 DataMovingInstructions 172
4.3.4.2 ArithmeticInstructions 174
4.3.4.3 LogicInstructions 176
4.3.4.4 ShiftandRotateInstructions 178
4.3.4.5 DataConversionInstructions 179
4.3.4.6 Bit-FieldProcessingInstructions 182
4.3.4.7 CompareandTestInstructions 186
4.3.4.8 ProgramFlowControlInstructions 187
4.3.4.9 SaturationInstructions 191
4.3.4.10 Exception-RelatedInstructions 193
4.3.4.11 SleepModeInstructions 194
4.3.4.12 MemoryBarrierInstructions 194
4.3.4.13 MiscellaneousInstructions 195
4.3.4.14 UnsupportedInstructions 196
4.4 ARM Cortex-M4SoftwareDevelopmentProcedures 196
4.5 UsingCLanguagetoDevelopARM Cortex-M4Microcontroller
Applications 197
4.5.1 TheStandardDataTypesUsedinIntrinsicFunctions 198
4.5.2 TheCMSIS-Core-SpecificIntrinsicFunctions 200
4.5.3 TheKeil ARM Compiler-SpecificIntrinsicFunctions 202
4.5.4 InlineAssembler 204