Physical Resource Allocation for On-Chip Power Delivery Systems

265 Pages·2011·3.4 MB·English

Physical Resource Allocation for On-Chip
Power Delivery Systems
by
Renatas Jakushokas
Submitted in Partial Fulfillment
of the
Requirements for the Degree
Doctor of Philosophy
Supervised by
Professor Eby G. Friedman
Department of Electrical and Computer Engineering
Arts, Sciences and Engineering
Edmund J. Hajim School of Engineering and Applied Sciences
University of Rochester
Rochester, New York
2011
ii
Dedication
This work is dedicated to my wife, Victoria Jakushokas, and my son, Daniel Noam
Jakushokas.
iii
Curriculum Vitae
Renatas Jakushokas was born in
Kaunas, Lithuania. He received the
B.Sc. degree (with honors) in electri-
calengineeringfromOrt-BraudeCollege,
Karmiel, Israel in 2005, and the M.S.
degree in electrical and computer engi-
neeringfromtheUniversityofRochester,
Rochester, New York in 2007. He is cur-
rently completing the Ph.D. degree in
electrical engineering at the University of Rochester.
He was previously an intern at Intrinsix Corporation, Fairport, New York in 2006,
working on Sigma Delta ADCs. In the summer of 2007, he interned with Eastman
Kodak Company, Rochester, New York, where he designed a high speed, precision
comparator for high performance ADCs. During the summer of 2008, he interned
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at Freescale Semiconductor Corporation, Tempe, Arizona, where he worked on de-
veloping a noise coupling estimation calculator, permitting the efficient evaluation
of diverse substrate isolation techniques. His research interests are in the areas of
power distribution, noise evaluation, signal integrity, substrate modeling/analysis,
and optimization techniques for high performance integrated circuit design.
Publications
Authored Book
1. R. Jakushokas, M. Popovich, A. V. Mezhiba, S. Kose, and E. G. Friedman,
Power Distribution Networks with On-Chip Decoupling Capacitors, Second Edi-
tion, Springer Publishers, 2011.
Journal Papers
2. R. Jakushokas and E. G. Friedman, “Multi-Layer Interdigitated Power Distri-
bution Networks,” IEEE Transactions on Very Large Scale Integration (VLSI)
Systems (in press).
3. R. Jakushokas and E. G. Friedman, “Resource Based Optimization for Simulta-
neous Shield and Repeater Insertion,” IEEE Transactions on Very Large Scale
Integration (VLSI) Systems, Vol. 18, No. 5, pp. 742-749, May 2010.
4. E. Salman, R. Jakushokas, E. G. Friedman, R. M. Secareanu, and O. L. Hartin,
“Methodology for Efficient Substrate Noise Analysis in Large Scale Mixed-
Signal Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, Vol. 17, No. 10, pp. 1405-1418, October 2009.
5. R. Jakushokas and E. G. Friedman, “Inductance Model of Interdigitated Power
and Ground Distribution Networks,” IEEE Transactions on Circuits and Sys-
tems II: Express Briefs, Vol. 56, No. 7, pp. 585-589, July 2009.
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Conference Papers
6. R. Jakushokas, E. Salman, E. G. Friedman, R. M. Secareanu, O. L. Hartin,
and C. L. Recker, “Compact Substrate Models for Efficient Noise Coupling and
Signal Isolation Analysis,” Proceedings of the IEEE International Symposium
on Circuits and Systems, pp. 2346 - 2349, May/June 2010.
7. R. Jakushokas and E. G. Friedman, “Globally Integrated Power and Clock
Distribution Network,” Proceedings of the IEEE International Symposium on
Circuits and Systems, pp. 1751 - 1754, May/June 2010.
8. R. Jakushokas and E. G. Friedman, “Methodology for Multi-Layer Interdigi-
tated Power and Ground Network Design,” Proceedings of the IEEE Interna-
tional Symposium on Circuits and Systems, pp. 3208 - 3211, May/June 2010.
9. R. Jakushokas and E. G. Friedman, “Line Width Optimization for Interdigi-
tated Power/Ground Networks,” Proceedings of the ACM/IEEE Great Lakes
Symposium on VLSI, pp. 329 - 334, May 2010.
10. R. Jakushokas and E. G. Friedman, “Minimizing Noise via Shield and Repeater
Insertion,” Proceedings of the IEEE International Symposium on Circuits and
Systems, pp. 2265 - 2268, May 2009.
11. E. Salman, R. Jakushokas, E. G. Friedman, R. M. Secareanu, and O L. Hartin,
“Contact Merging Algorithm for Efficient Substrate Noise Analysis in Large
Scale Circuits,” Proceedings of the ACM/IEEE Great Lakes Symposium on
VLSI, pp. 9 -14, May 2009.
12. R. Jakushokas and E. G. Friedman, “Simultaneous Shield and Repeater Inser-
tion,” Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 15
- 19, May 2009.
13. E. Salman, R. Jakushokas, E. G. Friedman, R. M. Secareanu, and O. L. Hartin,
“Input Port Reduction for Efficient Substrate Extraction in Large Scale IC’s,”
Proceedings of the IEEE International Symposium on Circuits and Systems, pp.
376 - 379, May 2008.
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Acknowledgments
My sincere gratitude is given to my advisor and mentor, Professor Eby G. Fried-
man for his continuous support, encouragement, and direction during the course of
my entire Ph.D. study. His knowledge, experience, insight, and enthusiasm instilled
in me a desire to originate and pursue my research studies. It was a great pleasure for
me to accomplish my thesis work under his supervision. What I know today about
the process of research, I learned from Professor Eby G. Friedman.
I would like to thank Professor Roman Sobolewski, Professor Zeljko Ignjatovic,
and Professor Peter Salzman for serving on my proposal and defense committees,
and Professor Michael L. Scott for chairing the defense committee. Your insightful
comments, critical reviews, and helpful advice enhanced my research and filled im-
portant gaps in my thesis dissertation. I want to also express my warm thanks to Dr.
Radu M. Secareanu, Dr. Olin L. Hartin, and Dr. Cynthia L. Recker from Freescale
Semiconductor, Dr. Mike Guidash, John Campton, and Dr. Weize Xu from Eastman
Kodak, and Dr. Muchadit Kozak and Gene Petilli from Intrinsix Corportion for your
guidance during three insightful summer internships.
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The diversity of professional and cultural backgrounds within the High Perfor-
mance Integrated Circuit Laboratory made my experience highly interesting and joy-
ful. I would like to thank previous and current members of the laboratory: Dr.
Guoqing Chen, Dr. Mikhail Popovich, Dr. Vasilis F. Pavlidis, Prof. Emre Salman,
Dr. Jonathan Rosenfeld, Ioannis Savidis, Selcuk Kose, Inna Vaisband, and Ravi
Patel. The long discussions on a variety of topics have expanded the scope of my
professional and personal knowledge. I thank RuthAnn Williams for her endless ef-
fort on my behalf, allowing me to focus my time on my research. I would also like to
acknowledge the staff in the Department of Electrical and Computer Engineering for
their assistance and support.
I express my thanks to all of my friends, who made my life in Rochester full of
joy and happiness. I will newer forget these amazing days. Most important, I owe a
special thanks to my parents, my wife’s parents, my wife Victoria, and my son Daniel
for their love, unconditional support, and endless encouragements. Without them, I
would never be in the place I am now.
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Abstract
The technology behind integrated circuits is growing rapidly with billions of de-
vices integrated on the same die. These devices operate at several gigahertz and
require tens of watts, with voltage levels below a volt. Highly complicated on-chip
networks manage and support the operation of these billions of devices. Resources,
such as metal, power, and area, are however limited; these resources must be effi-
ciently utilized. The increase in the number of metal layers within an integrated
circuit does not keep up with device scaling, creating challenges in global signaling,
synchronization, and power delivery. The objective is to address design, analysis,
and optimization challenges for highly complicated structures. Power distribution
networks, global signal networks, and monolithic substrate are considered in this
dissertation.
An effective impedance model of a monolithic substrate is developed within this
dissertation, achieving high accuracy in estimating power/ground noise characteris-
tics. A methodology for simultaneously inserting shields and repeaters is described,
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optimizing multiple resources for global signal interconnects. A closed-form model of
the self- and mutual inductance of an interdigitated power and ground distribution
network is described, providing less than 5% error for a typical power distribution
network. The optimal width of the metal lines that minimizes the impedance of the
power distribution network is determined, significantly enhancing the performance
of an integrated circuit. A design methodology is also described for a multi-layer
power distribution network, achieving enhanced reliability by equalizing the current
density over multiple metal layers. Furthermore, a novel link breaking methodology
for a mesh structured power distribution network is introduced, reducing coupling
noise while improving the maximum operating frequency, on average, by 12%. Fi-
nally, a globally integrated power and clock distribution network is presented which
utilizes a single network to distribute both global signals; thereby reducing the metal
requirement.
The performance of integrated circuits is highly affected by the power delivery
system. The primary focus of this dissertation is the development of design and
analysis methodologies for on-chip power delivery systems. Integrated circuits devel-
oped with these novel design methodologies will provide higher performance, while
simultaneously consuming less power, area, and metal.
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Contents
Dedication ii
Curriculum Vitae iii
Acknowledgments vi
Abstract viii
List of Tables xiv
List of Figures xvi
Foreword 1
1 Introduction 4
1.1 Global Interconnect: Friend or Foe . . . . . . . . . . . . . . . . . . . 7
1.2 Dissertation Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 Resources in Integrated Circuits 18
2.1 Design Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.1.1 Interconnect from a Resource Perspective . . . . . . . . . . . . 22
2.1.2 Power Supply System . . . . . . . . . . . . . . . . . . . . . . . 29
2.2 Optimization Process . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.2.1 Multi-Objective Optimization . . . . . . . . . . . . . . . . . . 36
2.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37