Logic Synthesis for Field-Programmable Gate Arrays

431 Pages·1995·9.29 MB·English

by  Rajeev Murgai

LOGIC SYNTHESIS
FOR
FIELD-PROGRAMMABLE
GATE ARRAYS
THE KLUWER INTERNATIONAL SERIES
IN ENGINEERING AND COMPUTER SCIENCE
VLSI, COMPUTER ARCHITECTURE AND
DIGITAL SIGNAL PROCESSING
Consulting Editor
Jonathan Allen
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LOGIC SYNTHESIS
FOR
FIELD-PROGRAMMABLE
GATE ARRAYS
by
Rajeev Murgai
Fujitsu Laboratories of America, Inc.
Robert K. Brayton
University of California, Berkeley
Alberto Sangiovanni-Vincentelli
University of California, Berkeley
~.
"
SPRINGER SCIENCE+BUSINESS MEDIA, LLC
Consulting Editor: Jonathan Allen, Massachusetts Institute of Technology
Library of Congress Cataloging-in-Publication Data
Murgai, Rajeev, 1966-
Logic synthesis for field-programmable gate arrays / by Rajeev
Murgai, Robert K. Brayton, Alberto Sangiovanni-Vincentelli.
p. cm.
Includes biographical references and index.
ISBN 978-1-4613-5994-4 ISBN 978-1-4615-2345-1 (eBook)
DOI 10.1007/978-1-4615-2345-1
1. Field programmable gate arrays. 2. Programmable array logic.
1. Brayton, Robert King. II. Sangiovanni-Vincentelli, Alberto.
III. Title.
TK7895.G36M87 1995
621.39'5--dc20 95-4866
CIP
Copyright © 1995 by Springer Science+Business Media New York
Originally published by Kluwer Academic Publishers in 1995
Softcover reprint of the hardcover 1 st edition 1995
AII rights reserved. No part of this publication may be reproduced, stored in
a retrieval system or transmitted in any form or by any means, mechanical,
photo-copying, recording, or otherwise, without the prior written permission of
the publisher, Springer Science+Business Media, LLC.
Printed on acidjree paper.
To
Mummy. Daddy. Didi. Puneet
for their selfless love. continuous support. immense patience. and unbounded
encouragement;
Ruth. Jane. Jim. Mike
for their love and support;
Andrea
who has been great company and has provided loving support in the many nights
spent working and studying together.
CONTENTS
PREFACE xiii
Part I INTRODUCTION 1
1 INTRODUCTION 3
1.1 Motivation 3
1.2 Designing VLSI Circuits 5
1.3 Programmable Devices: Field-Programmable Gate Arrays 7
1.3.1 Block Structures 9
1.3.2 Realizing Interconnections 13
1.3.3 Logic Synthesis for Field-Programmable Gate Arrays 14
1.4 Overview 15
2 BACKGROUND 19
2.1 Definitions 19
2.1.1 Logic Functions 19
2.1.2 Representing a Logic Function 29
2.1.3 Finite State Machines 31
2.2 Background: Logic Synthesis 34
2.2.1 Technology-IndependentOptimization 35
2.2.2 Technology Mapping 41
2.3 Logic Synthesis for Field-Programmable Gate Arrays 44
Part II LOOK-UP TABLE (LUT) ARCHITECTURES 49
3 MAPPING COMBINATIONAL LOGIC 51
3.1 Introduction 51
vii
viiiLOGIC SYNTHESIS FOR FIELD-PROGRAMMABLE GATE ARRAYS
3.2 History 53
3.2.1 Library-based Technology Mapping 53
3.2.2 mis-fpga 53
3.2.3 chortle 53
3.2.4 chortle-crf 54
3.2.5 Xmap 54
3.2.6 HYDRA 54
3.2.7 VISMAP 54
3.2.8 ASYL 54
3.2.9 mis-fpga (new) 55
3.2.10 TechMap 55
3.3 mis-fpga: Making an Infeasible Function Feasible 55
3.3.1 Functional Decomposition 56
3.3.2 Cube-packing 78
3.3.3 Cofactoring 97
3.3.4 Kernel Extraction 99
3.3.5 Technology Decomposition 99
3.3.6 Using Support Reduction to Achieve Feasibility 100
3.3.7 Summary 101
3.4 mis-fpga: Block Count Minimization 104
3.4.1 Covering 105
3.4.2 Support Reduction 121
3.5 mis-fpga: The Overall Algorithm 122
3.5.1 An Example 130
3.6 Other Mappers 134
3.6.1 Library-based Technology Mapping 134
3.6.2 chortle 135
3.6.3 chortle-crf 136
3.6.4 Xmap 139
3.6.5 VISMAP 140
3.6.6 TechMap 141
3.6.7 ASYL 143
3.7 Experimental Results 146
3.7.1 Description of Benchmarks 146
3.7.2 Decomposition 146
3.7.3 Decomposition and Block Count Minimization 146
Contents ix
3.7.4 Combining Everything: Using partial collapse 154
3.7.5 Relating Factored Form Literals and LUT s 155
3.7.6 Comparing mis-fpga with Other Mappers 155
3.8 Targeting Xilinx 3000 158
3.8.1 HYDRA 163
3.8.2 Experimental Results 166
3.9 Architecture-independent Mapping 166
3.9.1 TEMPT 170
3.9.2 Boolean Matching-based Approach 171
3.10 Synthesis for Routability 172
3.11 Discussion 175
4 LOGIC OPTIMIZATION 177
4.1 Introduction 177
4.2 Kernel extraction 179
4.3 Elimination 179
4.4 Simplification 179
4.4.1 Two-level Minimization 180
4.4.2 Are Minimum-cube and Minimum-literal SOPs Good for
Cube-packing? 182
4.4.3 Targeting Two-level Minimization for Cube-packing 184
4.4.4 The Overall Algorithm 189
4.4.5 Experimental Results 190
4.5 Discussion 192
5 COMPLEXITY ISSUES 195
5.1 Introduction 195
5.1.1 Definitions 196
5.2 Related Work 197
5.2.1 Prediction of LUT -count 197
5.2.2 Classical Bound Theory 198
5.3 New Results 201
5.3.1 Complexity Bound for n-input Functions 202
+
5.3.2 Implementing (m 1) -input Functions with m-LUTs 203
5.3.3 Complexity Bound Given an SOP Representation 222
5.3.4 Complexity Bound Given a Factored Form 223
xLOGIC SYNTHESIS FOR FIELD-PROGRAMMABLE GATE ARRAYS
5.4 Experiments 248
5.5 Discussion 252
6 MAPPING SEQUENTIAL LOGIC 255
6.1 Introduction 255
6.1.1 Overview of the Xilinx 3000 Architecture 257
6.1.2 Problem Statement 259
6.2 sis-fpga 260
6.2.1 mapJogether 261
6.2.2 map...separate 283
6.2.3 Comparing mapJogether and map...separate 289
6.3 Experimental Results 290
6.3.1 Different Encoding Schemes 294
6.4 Discussion 294
7 PERFORMANCE DIRECTED SYNTHESIS 299
7.1 Introduction 299
7.2 History 300
7.2.1 chortle-d 300
7.2.2 mis-fpga (delay) 300
7.2.3 flow-map 301
7.2.4 TechMap-L 301
7.3 Definitions 301
7.3.1 Problem Statement 302
7.4 mis-fpga (delay) 302
7.4.1 Placement-Independent (PI) Phase 302
7.4.2 Placement-Dependent (PD) Phase 304
7.5 Other Mappers 314
7.5.1 flow-map 314
7.5.2 chortle-d 315
7.6 Experimental Results 316
7.7 Discussion 321
Part III MULTIPLEXOR-BASED ARCHITECTURES 323
8 MAPPING COMBINATIONAL LOGIC 325
Contents xi
8.1 Introduction 325
8.2 History 326
8.2.1 Library-based Approaches 326
8.2.2 BOD-based Approaches 327
8.2.3 ITE-based Approaches 328
8.2.4 Boolean Matching-based Approaches 328
8.2.5 A Unified Algorithm 328
8.3 mis-fpga: Constructing Subject & Pattern Graphs Using BODs 329
8.3.1 ROBDDs 329
8.3.2 BODs 332
8.3.3 Loc.al versus Global Subject Graphs 332
8.3.4 Pattern Graphs 333
8.3.5 The Covering Algorithm 336
8.4 mis-fpga: A Unified Algorithm 337
8.5 The Matching Problem 341
8.5.1 The Matching Problem for act] 341
8.5.2 The Matching Problem for act2 349
8.6 mis-fpga: Constructing Subject & Pattern Graphs Using ITEs 356
8.6.1 Creating ITE for a Function with Disjoint Support Cubes 357
8.6.2 Creating ITE for a Unate Cover 358
8.6.3 Creating ITE for a Binate Cover 363
8.6.4 Comparing with Karplus's Construction 367
8.6.5 Pattern Graphs for ITE-based Mapping 367
8.7 Other Mappers 369
8.7.1 Amap 369
8.7.2 PROSERPINE 370
8.7.3 ASYL 375
8.8 Experimental Results 376
8.8.1 Without Iterative Improvement 376
8.8.2 Iterative Improvement Without Last Gasp 378
8.8.3 Iterative Improvement with Last Gasp 381
8.8.4 Using Global ROBDDs 381
8.8.5 Treating Node as the Image of the Network 385
8.8.6 Comparing Various Mappers 387
8.8.7 Using Multi-rooted ITEs 393
8.9 Discussion 393