LM97593 Dual ADC / Digital Tuner / AGC (Rev. B)

62 Pages·2014·4.6 MB·English

LM97593
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LM97593 Dual ADC / Digital Tuner / AGC
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FEATURES DESCRIPTION
1
• 100% SoftwareCompatiblewiththeCLC5903 The LM97593 Dual ADC / Digital Tuner / AGC IC is a
2 two channel digital downconverter (DDC) with
• PinCompatiblewiththeCLC5903Exceptfor
integrated 12-bit analog-to-digital converters (ADCs)
theAnalogInputandReferenceSection
and automatic gain control (AGC). The LM97593
• 123dBDynamicRangewithCLC5526DVGA further enhances TI’s Diversity Receiver Chipset
(200kHz) (DRCS) by integrating a wide-bandwidth dual ADC
core with the DDC. The complete DRCS includes one
• On-chipPrecisionReference
LM97593 Dual ADC / Digital Tuner / AGC and two
• UserProgrammableAGCwithEnhanced
CLC5526 digitally controlled variable gain amplifiers
PowerDetector (DVGAs). This system allows direct IF sampling of
• ChannelFiltersIncludeaFourthOrderCIC signals up to 300MHz for enhanced receiver
Followedby21-tapand 63-tapSymmetricFIRs performance and reduced system costs. A block
diagram for a DRCS-based narrowband
• FlexibleOutputFormats
communicationssystemisshowninFigure1.
• SerialandParallelOutputPorts
TheLM97593offershighdynamicrangedigitaltuning
• JTAGBoundaryScan
and filtering based on hard-wired digital signal
• 8-bitMicroprocessorInterface processing (DSP) technology. Each channel has
• 128pinPQFP independent tuning, phase offset, filter coefficients,
and gain settings. Channel filtering is performed by a
APPLICATIONS series of three filters. The first is a 4-stage Cascaded
Integrator Comb (CIC) filter with a programmable
• CellularBasestations decimation ratio from 8 to 2048. Next there are two
• GSM/GPRS/EDGE/GSMPhase2Receivers symmetricFIRfilters, a21-tapanda63-tap,both with
independent programmable coefficients. The first FIR
• SatelliteReceivers
filter decimates the data by 2, the second FIR
• WirelessLocalLoopReceivers decimates by either 2 or 4. Channel filter bandwidth
• DigitalCommunications at 52MSPS ranges from ±650kHz down to ±1.3kHz.
At 65MSPS, the maximum bandwidth increases to
KEY SPECIFICATIONS ±812kHz.
• InternalADCResolution:12Bits The LM97593’s AGC controller monitors the ADC
output and controls the ADC input signal level by
• SampleRate:65MSPS
adjusting the DVGA setting. AGC threshold,
• SNR(fIN=250MHz,11-bit,Nyquist):62dBFS deadband+hysteresis, and the loop time constant are
(typ) user defined. Total dynamic range of greater than
• SNR(f =250MHz,200kHz):83dBFS (typ) 123dB full-scale signal to noise in a 200kHz
IN
bandwidth can be achieved with the Diversity
• SFDR(f =250MHz,11-bit, Nyquist):68dBFS
IN ReceiverChipset.
(typ)
• FullPowerBandwidth:650MHz(typ)
• PowerConsumption:(65MSPS)560mW(typ)
1
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof
TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
Alltrademarksarethepropertyoftheirrespectiveowners.
2
PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2007–2013,TexasInstrumentsIncorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarilyincludetestingofallparameters.
LM97593
SNWS019B–JULY2007–REVISEDAPRIL2013 www.ti.com
Block Diagram 1
CLC5526 LM97593
(x2) SCK_IN
LC 12
SerialOutA/B
IF A DVGA ADC
SerialOutB
8 SCK
Dual Digital
SFS
Tuner/AGC
12 RDY
IF B DVGA ADC ParallelOutput[15:0]
LC ParallelOutputEnable
CLK ParallelSelect[2:0]
Figure1. DiversityReceiverChipset BlockDiagram
Connection Diagram
S
C
D
VDRCKNCNC VDDGNDDGND VDPD VAAGND VB-INVB+INVAVBCOMVBRPVBRNVREFAGND VAAGND VARNVARPVACOMVA+INVA-INAGND VAVAAGNDREFSEL/DGND VDDGND VDNCAGNDDRGND
3837363534333231302928272625242322212019181716151413121110987654321
39 128
VDR VDR
40 127
BGAIN[2] AGAIN[2]
41 126
BGAIN[1] AGAIN[1]
42 125
BGAIN[0] AGAIN[0]
43 124
~BSTROBE ~ASTROBE
44 123
D18GND VD18
45 122
~MR ~SCAN_EN
46 121
~SI ~TRST
47 120
DRGND D18GND
48 119
A[7] TCK
49 118
VD18 LM97593VH TMS
50 117
A[6] TDI
51 116
D18GND Dual Digital Tuner / AGC / ADC TDO
52 115
A[5] VD18
A[4] 53 (Top View) 114 POUT_SEL[0]
54 113
A[3] POUT_SEL[1]
55 112
A[2] POUT_SEL[2]
56 111
A[1] ~POUT_EN
57 110
A[0] DRGND
58 109
~WR POUT[0]
59 108
~RD POUT[1]
60 107
~CE VDR
61 106
DRGND POUT[2]
62 105
D[7] POUT[3]
63 104
D[6] POUT[4]
64 103
VDR D18GND
6566676869707172737475767778798081828384858687888990919293949596979899100101102
D18GNDD18GNDNCDRGNDD[5]D[4]D[3]D[2]D[1] VD18D[0]D18GNDRDYBOUT VDRSCKSFSAOUTDRGNDPOUT[15] VD18POUT[14]POUT[13]POUT[12]DRGNDPOUT[11]POUT[10] VDRPOUT[9]POUT[8]POUT[7]POUT[6]POUT[5]DRGNDSCK_INNCNC VDR
Figure2. LM97593VHPQFPPinout
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Block Diagram 2
AGAIN[2:0]
ASTROBE
12
VINA ADC_A MUX 14 CTuhnainnnge,l A OFourtmpuattter SCK_IN
A Channel Filters, and AOUT/BOUT
AGC BOUT
SCK
SFS
RDY
Channel B POUT[15:0]
VINB ADC_B 12 MUBX 14 TCuhnainnnge,l Filters, and PPOSEULT[_2E:0N]
AGC
TEST_REG BSTROBE
BGAIN[2:0]
Figure3. LM97593BlockDiagram
PINDESCRIPTIONSANDEQUIVALENTCIRCUITS
PinNo. Symbol EquivalentCircuit Description
ANALOGI/O
13 V A− Negativedifferentialinputsignalforthe'A'channel
IN AnalogInput
27 V B− Negativedifferentialinputsignalforthe'B'channel
IN
14 V A+ Positivedifferentialinputsignalforthe'A'channel
IN AnalogInput
26 V B+ Positivedifferentialinputsignalforthe'B'channel
IN
ReferenceSelectPin/ExternalReferenceVoltageInput
Inputdifferentialfullscaleswing=2*V
21 V Control/AnalogInput REF
REF V =V toV -0.3V: ReferenceVoltage=1.0V(Internal)
REF A A
V =0.8Vto1.5V: ReferenceVoltage=V (External)
REF REF
CommonModereferencevoltageforthe'A'channel
15 V A CommonModereferencevoltageforthe'B'channel
COM AnalogOutput
24 V B Thesepinsmaybeloadedto1mAforuseastemperaturestable1.5V
COM
references.
16 V A Upperreferencevoltageforthe'A'channel
RP AnalogOutput
23 V B Upperreferencevoltageforthe'B'channel
RP
17 V A Lowerreferencevoltageforthe'A'channel
RN AnalogOutput
22 V B Lowerreferencevoltageforthe'B'channel
RN
Thisisathree-statepin.V =V AorV B.
COM COM COM
REFSEL/DCS=AGND:theinternalreferenceisenabledanddutycycle
correctionisappliedtotheADCinputclock(CK).
8 REFSEL/DCS ControlInput REFSEL/DCS=V :theinternalreferenceisenabledandnoduty
COM
cyclecorrectionisappliedtotheADCinputclock(CK).
REFSEL/DCS=V :DCSison,theinternalreferenceisdisabled.Apply
A
A0.8-1.2VexternalreferencetotheV pin.
REF
DIGITALI/O
POWERDOWN,whenhighbothADCsarepowereddown,whenlow,
30 PD Input
bothADCsareenabled
MASTERRESET,Activelow
45 MR Input Resetsallregisterswithinthechip.ASTROBEandBSTROBEare
assertedduringMR.
SERIALOUTPUTDATA,Activehigh
The2'scomplementserialoutputdataistransmittedonthesepins,MSB
first.TheoutputbitschangeontherisingedgeofSCK(fallingedgeif
82 AOUT
Output SCK_POL=1)andshouldbecapturedonthefallingedgeofSCK(risingif
78 BOUT
SCK_POL=1).Thesepinsaretri-statedatpowerupandareenabledby
theSOUT_ENcontrolregisterbit.SeeFigure13andFigure75timing
diagrams.InDebugModeAOUT=DEBUG[1],BOUT=DEBUG[0].
127:125 AGAIN[2:0] OUTPUTDATATODVGA,Activehigh
Output
40:42 BGAIN[2:0] 3bitbusthatsetsthegainoftheDVGAdeterminedbytheAGCcircuit.
DVGASTROBE,Activelow
124 ASTROBE
Output StrobesthedataintotheDVGA.SeeFigure7andFigure82timing
43 BSTROBE
diagrams.
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PIN DESCRIPTIONSANDEQUIVALENTCIRCUITS(continued)
PinNo. Symbol EquivalentCircuit Description
SERIALDATACLOCK,Activehighorlow
Theserialdataisclockedoutofthechipbythisclock.Theactiveedgeof
theclockisuserprogrammable.Thispinistri-statedatpowerupandis
80 SCK Output enabledbytheSOUT_ENcontrolregisterbit.SeeFigure13and
Figure75timingdiagrams.InDebugModeoutputsanappropiateclock
forthedebugdata.IfRATE=0theinputCKdutycyclewillbereflectedto
SCK.
SERIALDATACLOCKINPUT,Activehighorlow
Databitsfromaserialdaisy-chainslaveareclockedintoaserialdaisy-
99 SCK_IN Input
chainmasteronthefallingedgeofSCK_IN(risingifSCK_POL=1onthe
slave).Tielowifnotused.
SERIALFRAMESTROBE,Activehighorlow
Theserialwordstrobe.Thisstrobedelineatesthewordswithintheserial
outputstreams.Thisstrobeisapulseatthebeginningofeachserial
81 SFS Output word(PACKED=0)oreachserialwordI/Qpair(PACKED=1).Thepolarity
ofthissignalisuserprogrammable.Thispinistri-statedatpowerupand
isenabledbytheSOUT_ENcontrolregisterbit.SeeFigure13and
Figure75timingdiagrams.InDebugModeSFS=DEBUG[2].
84,86:88, PARALLELOUTPUTDATA,Activehigh
90,91, Theoutputdataistransmittedonthesepinsinparallelformat.The
93:97, POUT[15:0] Output POUT_SEL[2:0]pinsselectoneofeight16-bitoutputwords.The
104:106, POUT_ENpinenablestheseoutputs.POUT[15]istheMSB.InDebug
108,109 ModePOUT[15:0]=DEBUG[19:4].
PARALLELOUTPUTDATASELECT,Activehigh
The16-bitoutputwordisselectedwiththese3pins.NotusedinDebug
112:114 POUT_SEL[2:0] Input Mode.Foraserialdaisy-chainmaster,POUT_SEL[2:0]becomeinputs
fromtheslave:POUT_SEL[2]=SFS ,POUT_SEL[1]=BOUT ,
SLAVE SLAVE
andPOUT_SEL[0]=AOUT .Tielowifnotused.
SLAVE
PARALLELOUTPUTENABLE.Activelow
111 POUT_EN Input Thispinenablesthechiptooutputtheselectedoutputwordonthe
POUT[15:0]pins.NotusedinDebugMode.Tiehighifnotused.
READYFLAG,Activehighorlow
Thechipassertsthissignaltoidentifythebeginningofanoutputsample
period(OSP).Thepolarityofthissignalisuserprogrammable.This
77 RDY Output
signalistypicallyusedasaninterrupttoaDSPchip,butcanalsobe
usedasastartpulsetodedicatedcircuitry.Thispinisactiveregardless
ofthestateofSOUT_EN.InDebugModeRDY=DEBUG[3].
INPUTCLOCK.Activehigh
Theclockinputtothechip.TheTheV AandV Banaloginputsignals
37 CK Input IN IN
aresampledontherisingedgeofthissignal.SIisclockedintothechip
ontherisingedgeofCK.
SYNCIN.Activelow
Thesyncinputtothechip.Thedecimationcounters,dither,andNCO
phasecanbesynchronizedbySI.Thissyncisclockedintothechipon
46 SI Input
therisingedgeofCK.Tiethispinhighifexternalsyncisnotrequired.All
sampledataisflushedbySI.ToproperlyinitializetheDVGAASTROBE
andBSTROBEareassertedduringSI.
DATABUS.Activehigh
62,63, Thisisthe8bitcontroldataI/Obus.Controlregisterdataisloadedinto
D[7:0] Input/Output
69:73,75 thechiporreadfromthechipthroughthesepins.Thechipwillonlydrive
outputdataonthesepinswhenCEislow,RDislow,andWRishigh.
ADDRESSBUS.Activehigh
Thesepinsareusedtoaddressthecontrolregisterswithinthechip.Each
48,50,52:57 A[7:0] Input ofthecontrolregisterswithinthechipareassignedauniqueaddress.A
controlregistercanbewrittentoorreadfrombysettingA[7:0]tothe
register’saddressandsettingCE,RD,andWRappropriately.
READENABLE.Activelow
59 RD Input Thispinenablesthechiptooutputthecontentsoftheselectedregister
ontheD[7:0]pinswhenCEisalsolow.
WRITEENABLE.Activelow
ThispinenablesthechiptowritethevalueontheD[7:0]pinsintothe
58 WR Input
selectedregisterwhenCEisalsolow.ThispincanalsofunctionasRD/
CEifRDisheldlow.SeeFigure15fordetails.
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PIN DESCRIPTIONSANDEQUIVALENTCIRCUITS(continued)
PinNo. Symbol EquivalentCircuit Description
CHIPENABLE.Activelow
Thiscontrolstrobeenablesthereadorwriteoperation.Thecontentsof
60 CE Input theregisterselectedbyA[7:0]willbeoutputonD[7:0]whenRDislow
andCEislow.IfWRislowandCEislow,thentheselectedregisterwill
beloadedwiththecontentsofD[7:0].
116 TDO Output TESTDATAOUT.Activehigh
117 TDI Input TESTDATAIN.Activehighwithpull-up
118 TMS Input TESTMODESELECT.Activehighwithpull-up
119 TCK Input TESTCLOCK.Activehigh.TielowifJTAGisnotused.
TESTRESET.Activelowwithpull-up
121 TRST Input AsynchronousresetforTAPcontroller.TielowortoMRifJTAGisnot
used.
SCANENABLE.Activelowwithpull-up
122 SCAN_EN Input Enablesaccesstointernalscanregisters.Tiehigh.Usedfor
manufacturingtestonly!
DigitalPowerSupplies
38,39,64,
79,92,102, V DDCOutputDriverPower I/OPowerSupply,3.3Vnominal.Quantity8.
DR
107,128
1,47,61,68,
83,89,98, DRGND DDCOutputDriverGround I/OGroundReturn.Quantity8.
110
49,74,85,
V DDCCorePower DSPDigitalCorePowerSupply,1.8Vnominal.Quantity5.
115,123 D18
49,74,85,
V DDCCorePower DSPDigitalCorePowerSupply,1.8Vnominal.Quantity5.
115,123 D18
44,51,65,
66,76,103, D18GND DDCCoreGround DSPDigitalCoreGroundReturn.Quantity7.
120
4,6,31,34 V ADCDigitalPower ADCDigitalLogicPowerSupply,3.3Vnominal.Quantity4.
D
5,7,32,33 DGND ADCDigitalGround ADCDigitalLogicGroundReturn.Quantity4.
AnalogPowerSupplies
10,11,19,
V ADCAnalogPower ADCAnalogPowerSupply,3.3Vnominal.Quantity5.
25,29 A
2,9,12,18,
AGND ADCAnalogGround ADCAnalogGroundReturn.Quantity6.
20,28
UnconnectedPins
3,35,36,67,
NC NC NotConnected.Thesepinsshouldbeleftfloating.
100,101
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Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam
duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.
Absolute Maximum Ratings(1)(2)(3)
ADCAnalog,DigitalandIOSupplyVoltages(V ,V andV ) −0.3Vto4.2V
A D DR
DifferencebetweenV ,V ,andV ≤100mV
A D DR
PositiveCoreSupplyVoltage(V ) −0.3Vto2.35V
D18
VoltageonAnyInputorOutputPin −0.3Vto(V +0.3V)
DR
(Nottoexceed4.2V)
InputCurrentatAnyPinotherthanSupplyPins (4) ±5mA
PackageInputCurrent (4) ±50mA
MaxJunctionTemp(T) +125°C
J
ThermalResistance(θ ) 39°C/W
JA
PackageDissipationatT =25°C(5) 3.2W
A
HumanBodyModel(1.5kΩ,100pF) 2000V
ESDSusceptibility(6)
MachineModel(0Ω,200pF) 200V
ChargeDeviceModel 750V
StorageTemperature −65°Cto+150°C
(1) AllvoltagesaremeasuredwithrespecttoGND=AGND=DGND=DRGND=0V,unlessotherwisespecified.
(2) AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.OperatingRatingsindicateconditionsfor
whichthedeviceisensuredtobefunctional,butdonotensurespecificperformancelimits.Forensuredspecificationsandtest
conditions,seetheElectricalCharacteristics.Theensuredspecificationsapplyonlyforthetestconditionslisted.Someperformance
characteristicsmaydegradewhenthedeviceisnotoperatedunderthelistedtestconditions.Operationofthedevicebeyondthe
maximumOperatingRatingsisnotrecommended.
(3) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityand
specifications.
(4) Whentheinputvoltageatanypinexceedsthepowersupplies(thatis,V <AGND,orV >V ),thecurrentatthatpinshouldbe
IN IN A
limitedto±25mA.The±50mAmaximumpackageinputcurrentratinglimitsthenumberofpinsthatcansafelyexceedthepower
supplieswithaninputcurrentof±25mAtotwo.
(5) ThemaximumallowablepowerdissipationisdictatedbyT ,thejunction-to-ambientthermalresistance,(θ ),andtheambient
J,max JA
temperature,(T ),andcanbecalculatedusingtheformulaP =(T -T )/θ .Thevaluesformaximumpowerdissipationlisted
A D,max J,max A JA
abovewillbereachedonlywhenthedeviceisoperatedinaseverefaultcondition(e.g.wheninputoroutputpinsaredrivenbeyondthe
powersupplyvoltages,orthepowersupplypolarityisreversed).Suchconditionsshouldalwaysbeavoided.
(6) HumanBodyModelis100pFdischargedthrougha1.5kΩresistor.MachineModelis220pFdischargedthrough0Ω.
Operating Ratings(1)(2)
SolderingprocessmustcomplywithTexasInstrument'sReflowTemperatureProfilespecifications.Refertohttp://www.ti.com/packaging(3)
OperatingTemperatureRange −40°C≤T ≤+85°C
A
ADCAnalog,DigitalandIOSupplyVoltages(V ,V andV ) +3.0Vto+3.6V
A D DR
DigitalCoreSupplyVoltage(VD18) +1.6Vto+2.0V
DifferenceBetweenAGND,DGND,DRGNDandD18GND ≤100mV
VoltageonAnyInputorOutputPin 0Vto+3.3V
V 1.0Vto2.0V
CM
ClockDutyCycle 30%to70%
(1) AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.OperatingRatingsindicateconditionsfor
whichthedeviceisensuredtobefunctional,butdonotensurespecificperformancelimits.Forensuredspecificationsandtest
conditions,seetheElectricalCharacteristics.Theensuredspecificationsapplyonlyforthetestconditionslisted.Someperformance
characteristicsmaydegradewhenthedeviceisnotoperatedunderthelistedtestconditions.Operationofthedevicebeyondthe
maximumOperatingRatingsisnotrecommended.
(2) AllvoltagesaremeasuredwithrespecttoGND=AGND=DGND=DRGND=0V,unlessotherwisespecified.
(3) Reflowtemperatureprofilesaredifferentforlead-freeandnon-lead-freepackages.
Reliability Information
TransistorCount 1.3million
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LM97593 Electrical Characteristics
Unlessotherwisespecified,thefollowingspecificationsapply:AGND=DGND=DRGND=D18GND=0V,V =V =V =
A D DR
+3.3V,V =+1.8V,InternalV =+1.0V,f =65MHz,V =V ,t =t =1ns,C =5pF/pin.TheADC’s11most
D18 REF CLK CM COM R F L
significantbitsobservedatthemixeroutputdebugtapwithNCO=0Hz.TypicalvaluesareforT =25°C.Boldfacelimits
A
applyforT ≤T ≤T .AllotherlimitsapplyforT =25°C.(1)(2)(3)
MIN A MAX A
Typical Units
Symbol Parameter Conditions (4) Limits (Limits)
STATICCONVERTERCHARACTERISTICS
ResolutionwithNoMissingCodes 11 Bits(min)
2 LSB(max)
INL IntegralNonLinearity(5) Ramp,EndPoint ±0.7
-2 LSB(min)
0.85 LSB(max)
DNL DifferentialNonLinearity Ramp,EndPoint ±0.3
-0.85 LSB(min)
V OffsetError −40°Cto+85°C -4.1 LSB
OFF
REFERENCEANDANALOGINPUTCHARACTERISTICS
1.0 V(min)
V CommonModeInputVoltage 1.5
CM
2.0 V(max)
V A
COM ReferenceOutputVoltage 1.5 V
V B
COM
V InputCapacitance(eachpintoGND) CKLOW 8 pF
CIN (VININ=1.5Vdc±0.5V) (6) CKHIGH 7 pF
0.8 V(min)
V ExternalReferenceVoltage(7) 1.0
REF
1.2 V(max)
ReferenceInputResistance 1 MΩ
(1) Theinputsareprotectedasshownbelow.InputvoltagemagnitudesaboveV orbelowGNDwillnotdamagethisdevice,provided
A
currentislimitedperNote(4).
(2) Toensureaccuracy,itisrequiredthat|V –V |≤100mVandseparatebypasscapacitorsareusedateachpowersupplypin.
A D
(3) WiththetestconditionforV =+1.0V(2V differentialinput),the12-BitLSBis488µV.
REF P-P
(4) TypicalfiguresareatT =25°Candrepresentmostlikelyparametricnormsatthetimeofproductcharacterization.Thetypical
A
specificationsarenotensured.TestLimitsarespecifiedtoTI'sAOQL(AverageOutgoingQualityLevel).
(5) IntegralNonLinearityisdefinedasthedeviationoftheanalogvalue,expressedinLSBs,fromthestraightlinethatpassesthrough
positiveandnegativefull-scale.
(6) Theinputcapacitanceisthesumofthepackage/pincapacitanceandthesampleandholdcircuitcapacitance.
(7) Optimumperformancewillbeobtainedbykeepingthereferenceinputinthe0.8Vto1.2Vrange.TheLM4051CIM3-ADJ(SOT-23
package)isrecommendedforexternalreferenceapplications.
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LM97593 Electrical Characteristics (continued)
Unlessotherwisespecified,thefollowingspecificationsapply:AGND=DGND=DRGND=D18GND=0V,V =V =V =
A D DR
+3.3V,V =+1.8V,InternalV =+1.0V,f =65MHz,V =V ,t =t =1ns,C =5pF/pin.TheADC’s11most
D18 REF CLK CM COM R F L
significantbitsobservedatthemixeroutputdebugtapwithNCO=0Hz.TypicalvaluesareforT =25°C.Boldfacelimits
A
applyforT ≤T ≤T .AllotherlimitsapplyforT =25°C.(1)(2)(3)
MIN A MAX A
Typical Units
Symbol Parameter Conditions (4) Limits (Limits)
DYNAMICCONVERTERCHARACTERISTICS
FPBW FullPowerBandwidth 650 MHz
66.2 dBFS
f =20MHz,V =-3dBFS
IN IN
SNR Signal-to-NoiseRatio f =249MHz,V =-3dBFS 63.7 dBFS
IN IN
f =249MHz,V =-9dBFS
IN IN 63.9 62.2 dBFS(min)
62.8 dBF
f =20MHz,V =-3dBFS
IN IN
SINAD Signal-to-NoiseandDistortion f =249MHz,V =-3dBFS 62.0 dBFS
IN IN
f =249MHz,V =-9dBFS
IN IN 63.4 60.4 dBFS(min)
10.6 Bits
f =20MHz,V =-3dBFS
EffectiveNumberofBits IN IN
ENOB f =249MHz,V =-3dBFS 10.0 Bits
(RelativetoFullScale) IN IN
f =249MHz,V =-9dBFS
IN IN 10.3 Bits(min)
-77.1 dBc
f =20MHz,V =-3dBFS
IN IN
THD TotalHarmonicDistortion f =249MHz,V =-3dBFS -57.9 dBc
IN IN
f =249MHz,V =-9dBFS
IN IN -64.6 -54.1 dBc(max)
-82.7 dBc
f =20MHz,V =-3dBFS
IN IN
H2 SecondHarmonicDistortion f =249MHz,V =-3dBFS -59.9 dBc
IN IN
f =249MHz,V =-9dBFS
IN IN -67.3 -59.3 dBc(max)
-91.7 dBc
f =20MHz,V =-3dBFS
IN IN
H3 ThirdHarmonicDistortion f =249MHz,V =-3dBFS -69.0 dBc
IN IN
f =249MHz,V =-9dBFS
IN IN -72.5 -56.8 dBc(min)
79.7 dBFS
f =20MHz,V =-3dBFS
IN IN
SFDR SpuriousFreeDynamicRange f =249MHz,V =-3dBFS 68.0 dBFS(min)
IN IN
f =249MHz,V =-9dBFS
IN IN 76.3 67.0 dBFS
f =246MHz,V =-15dBFS
1IN IN
IMD IntermodulationDistortion f =250MHz,V =-15dBFS -77.5 dBFS
2IN IN
(f +f =-9dBFS)
1IN 2IN
DynamicGainError -3dBFSreference,-50dBFStarget ±1.3 ±2 dB
INTERCHANNELCHARACTERISTICS
Channel-ChannelOffsetMatch 10MHz-1dBFSdriven ±0.2 %FS
Channel-ChannelGainMatch 10MHz-1dBFSdriven ±0.4 %FS
Crosstalk(AGCfixedat0dBgain,withAGC
249MHz-3dBFSdrivenchannel,50Ω 60(+42)
operatingthecrosstalkwillimproveatthe terminationmeasuredchannel (8) dBc
output)
CICOUTPUTCHARACTERISTICS
SNR Signal-to-NoiseRatio CICDecimation=8,NCO=11.1MHz 68.6 66.1 dBFS
([email protected]
SINAD Signal-to-NoiseandDistortion 68.5 66.1 dBFS
MHz),f =249MHzat-3dBFS,signal
IN
SFDR SpuriousFreeDynamicRange observedatF1InDebugtap 75.1 70.3 dBc
DDCOUTPUTCHARACTERISTICS
82(+42)
SNR Signal-to-NoiseRatio GSMFilterset,200kHzchannelBW, (8) dBFS
NCO=11.1MHz(248.9MHz
SINAD Signal-to-NoiseandDistortion @52MSPSaliasesto11.1MHz),f = 73 dBc
S
52MSPS,f =249MHzat-9dBFS
SFDR SpuriousFreeDynamicRange IN 90 dBc
(8) (+x)indicatestheadditionaldynamicrangeprovidedbytheAGC.TheDVGAinfrontoftheLM97593provides42dBofgainadjustment.
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LM97593 Electrical Characteristics (continued)
Unlessotherwisespecified,thefollowingspecificationsapply:AGND=DGND=DRGND=D18GND=0V,V =V =V =
A D DR
+3.3V,V =+1.8V,InternalV =+1.0V,f =65MHz,V =V ,t =t =1ns,C =5pF/pin.TheADC’s11most
D18 REF CLK CM COM R F L
significantbitsobservedatthemixeroutputdebugtapwithNCO=0Hz.TypicalvaluesareforT =25°C.Boldfacelimits
A
applyforT ≤T ≤T .AllotherlimitsapplyforT =25°C.(1)(2)(3)
MIN A MAX A
Typical Units
Symbol Parameter Conditions (4) Limits (Limits)
76(+42)
SNR Signal-to-NoiseRatio GSMFilterset,200kHzchannelBW, (9) dBFS
NCO=11.1MHz(248.9MHz
SINAD Signal-to-NoiseandDistortion @52MSPSaliasesto11.1MHz),f = 74 dBc
S
52MSPS,f =249MHzat-3dBFS
SFDR SpuriousFreeDynamicRange IN 90 dBc
79(+42)
SNR Signal-to-NoiseRatio GSMFilterset,200kHzchannelBW, (9) dBFS
NCO=11.1MHz(248.9MHz
SINAD Signal-to-NoiseandDistortion @65MSPSaliasesto11.1MHz),f = 71 dBc
S
65MSPS,f =249MHzat-9dBFS
SFDR SpuriousFreeDynamicRange IN 81 dBc
74(+42)
SNR Signal-to-NoiseRatio GSMFilterset,200kHzchannelBW, (9) dBFS
NCO=11.1MHz(248.9MHz
SINAD Signal-to-NoiseandDistortion @65MSPSaliasesto11.1MHz),f = 71 dBc
S
65MSPS,f =249MHzat-3dBFS
SFDR SpuriousFreeDynamicRange IN 80 dBc
(9) (+x)indicatestheadditionaldynamicrangeprovidedbytheAGC.TheDVGAinfrontoftheLM97593provides42dBofgainadjustment.
DC and Logic Electrical Characteristics
Unlessotherwisespecified,thefollowingspecificationsapply:AGND=DGND=DRGND=D18GND=0V,V =V =V =
A D DR
+3.3V,V =+1.8V,InternalV =+1.0V,f =65MHz,V =V ,t =t =TBDns,C =5pF/pin.CICDecimation=48,
D18 REF CLK CM COM R F L
F2Decimation=2.TypicalvaluesareforT =25°C.BoldfacelimitsapplyforT ≤T ≤T .AllotherlimitsapplyforT
A MIN A MAX A
=25°C.
Typical Units
Symbol Parameter Conditions (1) Limits (Limits)
V Voltageinputlow 0.7 V(max)
IL
V Voltageinputhigh 2.3 V(min)
IH
I Inputcurrent 20 µA
OZ
V Voltageoutputlow(I =7mA) 0.4 V(max)
OL OL
V Voltageoutputhigh(I =-7mA) 2.4 V(min)
OH OH
C Inputcapacitance 5.0 pF
IN
POWERSUPPLYCHARACTERISTICS
I ADCAnalogSupplyCurrent 65MSPS 96 121 mA(max)
A
I ADCAnalogSupplyCurrent 52MSPS 84 mA
A
I ADCDigitalSupplyCurrent 65MSPS 24 28 mA(max)
D
I ADCDigitalSupplyCurrent 52MSPS 20 mA
D
I DigitalOutputSupplyCurrent (2) 65MSPS 14 18 mA(max)
DR
I DigitalOutputSupplyCurrent (2) 52MSPS 10 mA
DR
I DigitalCoreSupplyCurrent 65MSPS 67 78 mA(max)
D18
I DigitalCoreSupplyCurrent 52MSPS 53 mA
D18
P TotalPowerDissipation GSMSet,65MSPS 560 793 mW(max)
D65
P TotalPowerDissipation GSMSet,52MSPS 485 mW
D52
RejectionofFull-ScaleErrorwithVA=
PSRR PowerSupplyRejectionRatio dB
3.0Vvs.3.6V
(1) TypicalfiguresareatT =25°Candrepresentmostlikelyparametricnormsatthetimeofproductcharacterization.Thetypical
A
specificationsarenotensured.TestLimitsarespecifiedtoTI'sAOQL(AverageOutgoingQualityLevel).
(2) I isthecurrentconsumedbytheswitchingoftheoutputdriversandisprimarilydeterminedbyloadcapacitanceontheoutputpins,
DR
thesupplyvoltage,V ,andtherateatwhichtheoutputsareswitching(whichissignaldependent).I =V (C xf +C xf +....C x
DR DR DR 0 0 1 1 11
f )whereV istheoutputdriverpowersupplyvoltage,C istotalcapacitanceontheoutputpin,andf istheaveragefrequencyat
11 DR n n
whichthatpinistoggling.
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AC Electrical Characteristics
Unlessotherwisespecified,thefollowingspecificationsapply:AGND=DGND=DRGND=D18GND=0V,V =V =V =
A D DR
+3.3V(±10%),V =+1.8V(±10%),InternalV =+1.0V,f =65MHz,V =V ,t =t =1ns,C =5pF/pin.CIC
D18 REF CLK CM COM R F L
Decimation=48,F2Decimation=2.TypicalvaluesareforT =25°C.BoldfacelimitsapplyforT ≤T ≤T .Allother
A MIN A MAX
limitsapplyforT =25°C.(1)
A
Typical
Symbol Parameter(CL=50pF) Min (2) Max Units
ClockInput
F Clock(CK)Frequency(Figure6) 20 65 MHz
CK
t CKdutycycle,DCSoff(Figure6) 40 60 %
CKDC
t CKriseandfalltimes(V toV )(Figure6) 2 ns
RF IL IH
NCOTuningResolution 0.02 Hz
NCOPhaseResolution 0.005 o
ControlInterface
t MRActiveTime(Figure4) 4 CKperiods
MRA
t MRInactivetofirstControlPortAccess(Figure4) 10 CKperiods
MRIC
t MRSetupTimetoCK(Figure4) 6 ns
MRSU
t MRHoldTimefromCK(Figure4) 2 ns
MRH
t SISetupTimetoCK(Figure5) 6 ns
SISU
t SIHoldTimefromCK(Figure5) 2 ns
SIH
t SIPulseWidth(Figure5) 4 CKperiods
SIW
DVGAInterface
t A|BSTROBEInactivePulseWidth(Figure7) 2 CKperiods
STIW
t A|BGAINsetupbeforeA|BSTROBE(Figure7) 6 ns
GSTB
ParallelOutputInterface
t POUT_ENActivetoPOUT[15:0]Valid(Figure9) 12 ns
OENV
t POUT_ENInactivetoPOUT[15:0]Tri-State(Figure9) 10 ns
OENT
t PSEL[2:0]toPOUT[15:0]Valid(Figure10) 13 ns
SELV
t RDYtoPOUT[15:0]NewValueValid(Note5)(Figure11) 7 ns
POV
t SCKtoPOUT[15:0],RDY,SFS,AOUT,BOUTValid(Figure12) 4 ns
DBG
SerialInterface
t SCKtoSFSValid(Note3)(Figure13) -2 1.6 3.5 ns
SFSV
t SCKtoA|BOUTValid(Note4)(Figure13) -2 1.7 3.5 ns
OV
t RDYPulseWidth(Figure13) 2 CKperiods
RDYW
t PSEL[2:0]SetupTimetoSCK_IN(Figure8) 3 1.4 ns
DCMSU
t PSEL[2:0]HoldTimefromSCK_IN(Figure8) 0.5 -0.9 ns
DCMH
t SCKtoRDYvalid(Figure13) -3 1.8 4 ns
RDYV
JTAGInterface
t PropagationDelayTCKtoTDO(Figure14) 25 ns
JPCO
t PropagationDelayTCKtoDataOut(Figure14) 35 ns
JSCO
t DisableTimeTCKtoTDO(Figure14) 25 ns
JPDZ
t DisableTimeTCKtoDataOut(Figure14) 35 ns
JSDZ
t EnableTimeTCKtoTDO(Figure14) 0 25 ns
JPEN
t EnableTimeTCKtoDataOut(Figure14) 0 35 ns
JSEN
t SetupTimeDatatoTCK(Figure14) 10 ns
JSSU
t SetupTimeTDI,TMStoTCK(Figure14) 10 ns
JPSU
t HoldTimeDatatoTCK(Figure14) 45 ns
JSH
t HoldTimeTCKtoTDI,TMS(Figure14) 45 ns
JPH
(1) TimingspecificationsaretestedatTTLlogiclevels,V =0.4VforafallingedgeandV =2.4Vforarisingedge.
IL IH
(2) TypicalfiguresareatT =25°Candrepresentmostlikelyparametricnormsatthetimeofproductcharacterization.Thetypical
A
specificationsarenotensured.TestLimitsarespecifiedtoTI'sAOQL(AverageOutgoingQualityLevel).
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