Table Of ContentLecture Notes in Electrical Engineering 454
Franco Fummi
Robert Wille
Editors
Languages, Design
Methods, and
Tools for Electronic
System Design
Selected Contributions from FDL 2016
Lecture Notes in Electrical Engineering
Volume 454
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Franco Fummi (cid:129) Robert Wille
Editors
Languages, Design Methods,
and Tools for Electronic
System Design
Selected Contributions from FDL 2016
123
Editors
FrancoFummi RobertWille
UniversityofVerona JohannesKeplerUniversityLinz
Verona,Italy Linz,Austria
ISSN1876-1100 ISSN1876-1119 (electronic)
LectureNotesinElectricalEngineering
ISBN978-3-319-62919-3 ISBN978-3-319-62920-9 (eBook)
DOI10.1007/978-3-319-62920-9
LibraryofCongressControlNumber:2017950291
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Foreword
The increasing integration and complexity of electronic system design requires
constantevolutionoftheusedlanguagesaswellasassociateddesignmethodsand
tools. The Forum on specification and Design Languages (FDL) is an established
internationalforumdevotedtothedisseminationofresearchresults,practicalexpe-
riences, and new ideas in the application of specification, design, and verification
languages.Itconsidersdescriptionsmeansforthedesign,modeling,andverification
of integrated circuits, complex hardware/software embedded systems, and mixed-
technologysystems.
FDL is the main platform to present and discuss new trends as well as recent
workinthisdomain.The2016editionofFDLwasaninterestingandlivelymeeting
thankstothecommitmentoftheauthorsandpresenters.
This book is devoted to FDL 2016 and contains the papers that were evaluated
best by both the members of the program committee as well as the participants of
the forum which took place in September 2016 in Bremen, Germany. It reflects
thereby the wide range of topics which have been covered at this event. The
selected contributions particularly highlighttheincreasing roleof AMSlanguages
and verification tools—as essential, e.g., in the fields of smart systems and IoT,
where devices are the result of a deep integration of heterogeneous analog and
digital components. The papers propose state-of-the-art methodologies for their
design,verification,andsafetyanalysis.Bythis,theportfolioofpapersinthisbook
providesanin-depthviewonthecurrentdevelopmentsinourdomainwhichsurely
willhaveasignificantimpactinthefuture.
Wewouldliketothankallauthorsfortheircontributionsaswellasthemembers
of the program committee and the external reviewers for their hard work in
evaluatingthesubmissions.SpecialthanksgotoRolfDrechslerandhisteamfrom
theUniversityofBremen,whowereresponsibleforasplendidorganizationofFDL
v
vi Foreword
2016, as well as Sophie Cerisier from the Electronic Chips and Systems design
Initiative (ECSI). Finally, we would like to thank Springer for making this book
possible.
Verona,Italy FrancoFummi
Linz,Austria RobertWille
May2017
Contents
Knowing Your AMS System’s Limits: System Acceptance
Region Exploration by Using Automated Model Refinement
andAcceleratedSimulation..................................................... 1
GeorgGläser,Hyun-SekLukasLee,MarkusOlbrich,andErichBarke
DesigningReliableCyber-PhysicalSystems .................................. 15
GadiAleksandrowicz,EliArbel,RoderickBloem,TimonD.terBraak,
SergeiDevadze,GoerschwinFey,MaksimJenihhin,ArturJutman,
HansG.Kerkhoff,RobertKönighofer,ShlomitKoyfman,JanMalburg,
ShiriMoran,JaanRaik,GerardRauwerda,HeinzRiener,FranzRöck,
KonstantinShibin,KimSunesen,JinboWan,andYongZhao
OntheApplicationofFormalFaultLocalizationtoAutomated
RTL-to-TLMFaultCorrespondenceAnalysisforFastandAccurate
VP-BasedErrorEffectSimulation:ACaseStudy ........................... 39
VladimirHerdt,HoangM.Le,DanielGroße,andRolfDrechsler
Error-BasedMetricforCross-LayerCutDetermination ................... 59
A.Rafiev,F.Xia,A.Iliasov,R.Gensh,A.Aalsaud,A.Romanovsky,
andA.Yakovlev
Feature-BasedStateSpaceCoverageMetricforAnalogCircuit
Verification........................................................................ 83
AndreasFürtig,SebastianSteinhorst,andLarsHedrich
Error-FreeNear-ThresholdAdiabaticCMOSLogicinthePresence
ofProcessVariation.............................................................. 103
YueLuandTomJ.Kazmierski
Index............................................................................... 115
vii
Knowing Your AMS System’s Limits: System
Acceptance Region Exploration by Using
Automated Model Refinement and Accelerated
Simulation
GeorgGläser,Hyun-SekLukasLee,MarkusOlbrich,andErichBarke
Abstract Virtual prototyping of Analog/Mixed-Signal (AMS) systems is a key
concerninmodernSoCverification.Achievingfirst-timerightdesignsisachalleng-
ingtask:Everyrelevantfunctionalandnon-functionalpropertyhastobeexamined
throughout the complete design process. Many faulty designs have been verified
carefully before tape out but are still missing at least one low-level effect which
arisesfrominteractionbetweenoneormoresystemcomponents.Sincetheseextra-
functionaleffectsareoftenneglectedonsystemlevel,thedesigncannotberectified
in early design stages or verified before fabrication. We introduce a method to
determine system acceptance regions tackling this challenge: We include extra-
functional effects into the system models, and we investigate their behavior with
parallelsimulationsincombinationwithanacceleratedanalogsimulationscheme.
The accelerated simulation approach is based on local linearizations of nonlinear
circuits, which result in piecewise-linear systems. High-level simulation speed-
up is achieved by avoiding numerical integration and using parallel computing.
This approach is fully automated requiring only a circuit netlist. To reduce the
overallnumberofsimulations,weuseanadaptivesamplingalgorithmforexploring
systemsacceptanceregionswhichindicatefeasibleandcriticaloperatingconditions
oftheAMSsystem.
Keywords Parameter space (cid:129) Acceptance region (cid:129) Piece-wise linear (cid:129) Simula-
tion (cid:129) Modeling (cid:129) Bordersearch (cid:129) Mixed-signal (cid:129) Virtual prototyping (cid:129) Auto-
mated model refinement (cid:129) Design automation (cid:129) Extra-functional properties (cid:129)
Acceleratedsimulation (cid:129) Systemlevel (cid:129) Verification
G.Gläser((cid:2))
IMMSInstitutfürMikroelektronik-undMechatronik-SystemegemeinnützigeGmbH,
Ehrenbergstr.27,D-98693Ilmenau,Germany
e-mail:[email protected]
H.-S.L.Lee(cid:129)M.Olbrich(cid:129)E.Barke
InstitutfürMikroelektronischeSysteme,Applestr.4,D-30167Hannover,Germany
e-mail:[email protected];[email protected];
[email protected]
©SpringerInternationalPublishingAG2018 1
F.Fummi,R.Wille(eds.),Languages,DesignMethods,andTools
forElectronicSystemDesign,LectureNotesinElectricalEngineering454,
DOI10.1007/978-3-319-62920-9_1
2 G.Gläseretal.
1 Introduction
Many carefully verified designs fail due to flaws which neither the design nor the
verificationengineerhasidentified.AsshowninFig.1thedesignflawmighteven
be located outside the functional behavior of the system’s components: Distorted
supplies or parasitic couplings can raise severe problems that are only visible in
certain conditions but are crucial to the overall functionality. Such design flaws
are usually not covered by abstract system-level models since they neglect low-
level effects. Within this contribution, we consider a common DC–DC converter
circuit as shown in Fig.2 for demonstration. This hysteretic current-mode buck
converter will always be stable in simulation assuming idealized models and
reference voltages [1]. However, its stability can be influenced by distortions not
visibleonsystemlevel.Forexample,distortionsduetoground-bounceorcrosstalk
fromthesupplytothereferencevoltagesmaycausemalfunction.Uncoveringthese
interactions by simulation on transistor or layout level is virtually impossible for
such a demonstrator or even more complex systems due to enormous computing
times.
Fig.1 System-level
verificationtargetsat
verifyingallfunctional
propertiesusingabstract
models
Fig.2 Hysteretic current-mode buck converter as application scenario. The output current is
determinedviareferencesgeneratedbydigital-to-analogconverters(DAC)
