Handbook of Digital Techniques for High-Speed Design: Design Examples, Signaling and Memory Technologies, Fiber Optics, Modeling, and Simulation to Ensure Signal Integrity

976 Pages·2004·20.03 MB·English

by  Tom Granberg

HANDBOOK OF DIGITAL
TECHNIQUES FOR
HIGH-SPEED DESIGN
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Essential Electronic Design Automation (EDA)
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Signal Integrity: Simplified
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Signal Integrity Issues and Printed Circuit Board Design
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High-Speed Signal Propagation: Advanced Black Magic
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Genetic Algorithms for VLSI Design, Layout, and Test Automation
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From ASICs to SOCs: A Practical Approach
Farzad Nekoogar
Timing Verification of Application-Specific Integrated Circuits
(ASICs)
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Design Verification with e
David Pellerin and Douglas Taylor
VHDL Made Easy!
Christopher T. Robertson
Printed Circuit Board Designer’s Reference: Basics
Chris Rowen
Engineering the Complex SOC
Frank Scarpino
VHDL and AHDL Digital System Implementation
Wayne Wolf
FPGA-Based System Design
Wayne Wolf
Modern VLSI Design: System-on-Chip Design, Third Edition
Kiat-Seng Yeo, Samir S. Rofail, and Wang-Ling Goh
CMOS/BiCMOS ULSI: Low Voltage, Low Power
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with Interconnects and Packages
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Verilog Designer’s Library
HANDBOOK OF DIGITAL
TECHNIQUES FOR
HIGH-SPEED DESIGN
Design Examples, Signaling and Memory
Technologies, Fiber Optics, Modeling and
Simulation to Ensure Signal Integrity
Tom Granberg, Ph.D.
PRENTICE HALL PTR
UPPER SADDLE RIVER, NJ 07458
WWW.PHPTR.COM
Library of Congress Cataloging-in-Publication Data
Granberg, Tom.
Handbook of digital techniques for high-speed design : design examples, signaling and memory
technologies, fiber optics, modeling and simulation to ensure signal integrity / Tom Granberg.
p. cm.
Includes bibliographical references and index.
ISBN 0-13-142291-X
1. Signal processing--Digital techniques--Handbooks, manuals, etc. 2. Very high speed integrated
circuits--Design and construction--Handbooks, manuals, etc. I. Title.
TK5102.9.G72 2004
621.382’2--dc22
2004046509
Editorial/production supervision: Vanessa Moore
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© 2004 by Pearson Education, Inc.
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Figures, tables, and text reprinted with permission from “IEEE Std. 802.3ae Apr 2002, XGMII Extender Sublayer
(XGXS) and 10 Gigabit Attachment Unit Interface (XAUI),” Copyright April 2002 by IEEE. The IEEE disclaims
any responsibility or liability resulting from the placement and use in the described manner.
FASL, the FASL logo, Spansion, and combinations thereof as well as certain other marks listed at http://www.amd.com/
legal/trademarks.html are trademarks of FASL LLC.
The circuit diagram and eye diagram on the front cover of this textbook were taken from reference [Mot02a], BR1570/D,
WarpLink Reference Design Platform White Paper. Copyright of Motorola. Used by permission. In the circuit diagram
on the front cover, the cubical blocks labelled “Via” represent via effects due to stubs.
Other company and product names mentioned herein are the trademarks or registered trademarks of their respective
owners.
All rights reserved. No part of this book may be reproduced, in any form or by any means, without permission in writing
from the publisher.
Printed in the United States of America, Second Printing, August 2004
ISBN 0-13-142291-X
Pearson Education Ltd.
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To
Randy Kriegh,
the world’s nicest boss
and a man of high personal integrity.
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CONTENTS
Preface xxxvii
How This Book Is Organized xxxvii
This Textbook Was Written with Educational Institutions in Mind xxxix
University Courses for Which This Book Is Suitable xl
Solutions Manual Is Available xl
Cash for Identifying Textbook Errors xl
How This Book Was Prepared xli
Personal Acknowledgments xli
Technical Acknowledgments xliii
Part 1 Introduction 1
Chapter 1 Trends in High-Speed Design 3
1.1 Everything Keeps Getting Faster and Faster! 3
1.2 Emerging Technologies and Industry Trends 6
1.2.1 Major Drivers of Printed Circuit Board (PCB) Technology 6
1.2.2 Drivers of Innovation 6
1.2.3 I/O Signaling Standards 7
1.2.4 Web Site as Retailer 8
1.2.5 Memories 8
1.2.6 On-Die Terminations 9
1.3 Trends in Bus Architecture 9
1.3.1 Moving from Parallel to Serial 10
1.3.2 The Power of Tools 11
1.3.3 ASSPs and ASMs 12
1.4 High-Speed Design as an Offshoot from Microwave Theory 12
1.5 Background Disciplines Needed for High-Speed Design 13
1.5.1 High-Speed Conferences and Forums 13
1.6 Book Organization 14
1.7 Exercises 15
ix
x Contents
Chapter 2 ASICs, Backplane Configurations,
and SerDes Technology 17
2.1 Application-Specific Integrated Circuits (ASICs) 17
2.2 Bus Configurations 18
2.2.1 Single-Termination Multidrop 18
2.2.2 Double-Termination Multidrop 19
2.2.3 Data Distribution with Point-to-Point Links 19
2.2.4 Multipoint 20
2.2.5 Switch Matrix 20
Mesh and Fabric Point-to-Point Bus Architectures 21
2.3 SerDes Devices 21
2.3.1 SerDes Device Fundamentals 21
2.3.2 SerDes at 5 Gbps 24
2.3.3 SerDes Multibit Signal Encoding 26
2.4 Electrical Interconnects vs. Fiber Optics 26
2.5 Subtleties of Device Families 27
2.5.1 Logic vs. Interface Families 27
2.5.2 Murky Device Categories 28
2.5.3 Logic Family vs. Signaling Standard 28
2.6 EDN Magazine’s Microprocessor Directory 28
2.7 Exercises 29
Chapter 3 A Few Basics on Signal Integrity 31
3.1 Transmission Lines and Termination 31
3.1.1 Transmission Line Equations 31
3.1.2 Reflection Coefficients, Lattice Diagrams, and Termination 34
3.2 Important High-Speed Concepts 38
3.2.1 Rise Time and Edge Rate 38
3.2.2 Length of the Rising Edge 39
3.2.3 Knee Frequency 40
3.2.4 Single-Ended vs. Differential Transmission 40
3.2.5 Fast Edge Rate Effects 41
3.2.6 Parasitics 42
3.3 High-Frequency Effects: Skin Effect, Crowding Effect, Return Path
Resistance, and Frequency-Dependent Dielectric Loss 42
3.4 Jitter Measurements Using Eye Patterns 43
3.5 BER Testing 46
3.6 Exercises 47