FPGA-based Implementation of Signal Processing Systems

488 Pages·2017·15.14 MB·English

by  Roger Woods

FPGA-based Implementation
of Signal Processing Systems
Second Edition
Roger Woods
Queen’s University, Belfast, UK
John McAllister
Queen’s University, Belfast, UK
Gaye Lightbody
University of Ulster, UK
Ying Yi
SN Systems — Sony Interactive Entertainment, UK
This edition first published 2017
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Library of Congress Cataloging-in-Publication Data
Names: Woods, Roger, 1963- author. | McAllister, John, 1979- author. |
Lightbody, Gaye, author. | Yi, Ying (Electrical engineer), author.
Title: FPGA-based implementation of signal processing systems / Roger Woods,
John McAllister, Gaye Lightbody, Ying Yi.
Description: Second editon. | Hoboken, NJ : John Wiley & Sons Inc., 2017. |
Revised edition of: FPGA-based implementation of signal processing systems /
Roger Woods … [et al.]. 2008. | Includes bibliographical references and index.
Identifiers: LCCN 2016051193 | ISBN 9781119077954 (cloth) | ISBN 9781119077978 (epdf) |
ISBN 9781119077961 (epub)
Subjects: LCSH: Signal processing--Digital techniques. | Digital integrated
circuits. | Field programmable gate arrays.
Classification: LCC TK5102.5 .F647 2017 | DDC 621.382/2--dc23 LC record available at
https://lccn.loc.gov/2016051193
Cover Design: Wiley
Cover Image: © filo/Gettyimages;
(Graph) Courtesy of the authors
The book is dedicated by the main author to his wife, Pauline, for all for her support and
care, particularly over the past two years.
The support from staff from the Royal Victoria Hospital and Musgrave Park Hospital is
greatly appreciated.
CONTENTS
Preface
List of Abbreviations
1 Introduction to Field Programmable Gate Arrays
1.1 Introduction
1.2 Field Programmable Gate Arrays
1.3 Influence of Programmability
1.4 Challenges of FPGAs
Bibliography
2 DSP Basics
2.1 Introduction
2.2 Definition of DSP Systems
2.3 DSP Transformations
2.4 Filters
2.5 Adaptive Filtering
2.6 Final Comments
Bibliography
3 Arithmetic Basics
3.1 Introduction
3.2 Number Representations
3.3 Arithmetic Operations
3.4 Alternative Number Representations
3.5 Division
3.6 Square Root
3.7 Fixed-Point versus Floating-Point
3.8 Conclusions
Bibliography
4 Technology Review
4.1 Introduction
4.2 Implications of Technology Scaling
4.3 Architecture and Programmability
4.4 DSP Functionality Characteristics
4.5 Microprocessors
4.6 DSP Processors
4.7 Graphical Processing Units
4.8 System-on-Chip Solutions
4.9 Heterogeneous Computing Platforms
4.10 Conclusions
Bibliography
5 Current FPGA Technologies
5.1 Introduction
5.2 Toward FPGAs
®
5.3 Altera Stratix V and 10 FPGA Family
TM
5.4 Xilinx Ultrascale /Virtex-7 FPGA families
5.5 Xilinx Zynq FPGA Family
5.6 Lattice iCE40isp FPGA Family
5.7 MicroSemi RTG4 FPGA Family
5.8 Design Stratregies for FPGA-based DSP Systems
5.9 Conclusions
Bibliography
6 Detailed FPGA Implementation Techniques
6.1 Introduction
6.2 FPGA Functionality
6.3 Mapping to LUT-Based FPGA Technology
6.4 Fixed-Coefficient DSP
6.5 Distributed Arithmetic
6.6 Reduced-Coefficient Multiplier
6.7 Conclusions
Bibliography
7 Synthesis Tools for FPGAs
7.1 Introduction
7.2 High-Level Synthesis
7.3 Xilinx Vivado
7.4 Control Logic Extraction Phase Example
7.5 Altera SDK for OpenCL
7.6 Other HLS Tools
7.7 Conclusions
Bibliography
8 Architecture Derivation for FPGA-based DSP Systems
8.1 Introduction
8.2 DSP Algorithm Characteristics
8.3 DSP Algorithm Representations
8.4 Pipelining DSP Systems
8.5 Parallel Operation
8.6 Conclusions
Bibliography
9 Complex DSP Core Design for FPGA
9.1 Introduction
9.2 Motivation for Design for Reuse
9.3 Intellectual Property Cores
9.4 Evolution of IP cores
9.5 Parameterizable (Soft) IP Cores
9.6 IP Core Integration
9.7 Current FPGA-based IP cores
9.8 Watermarking IP
9.9 Summary
Bibliography
10 Advanced Model-Based FPGA Accelerator Design
10.1 Introduction
10.2 Dataflow Modeling of DSP Systems
10.3 Architectural Synthesis of Custom Circuit Accelerators from DFGs
10.4 Model-Based Development of Multi-Channel
Dataflow Accelerators
10.5 Model-Based Development for Memory-Intensive Accelerators
10.6 Summary
Notes
Bibliography
11 Adaptive Beamformer Example
11.1 Introduction to Adaptive Beamforming
11.2 Generic Design Process
11.3 Algorithm to Architecture
11.4 Efficient Architecture Design
11.5 Generic QR Architecture
11.6 Retiming the Generic Architecture
11.7 Parameterizable QR Architecture
11.8 Generic Control
11.9 Beamformer Design Example
11.10 Summary
Bibliography
12 FPGA Solutions for Big Data Applications
12.1 Introduction
12.2 Big Data
12.3 Big Data Analytics
12.4 Acceleration
12.5 k-Means Clustering FPGA Implementation
12.6 FPGA-Based Soft Processors
12.7 System Hardware
12.8 Conclusions
Bibliography
13 Low-Power FPGA Implementation
13.1 Introduction
13.2 Sources of Power Consumption
13.3 FPGA Power Consumption
13.4 Power Consumption Reduction Techniques
13.5 Dynamic Voltage Scaling in FPGAs
13.6 Reduction in Switched Capacitance
13.7 Final Comments
Bibliography
14 Conclusions
14.1 Introduction
14.2 Evolution in FPGA Design Approaches
14.3 Big Data and the Shift toward Computing
14.4 Programming Flow for FPGAs
14.5 Support for Floating-Point Arithmetic
14.6 Memory Architectures
Bibliography
Index
EULA
List of Tables
Chapter 1
Table 1.1
Chapter 3
Table 3.1
Table 3.2
Table 3.3
Table 3.4
Table 3.5
Table 3.6
Table 3.7
Table 3.8
Table 3.9
Table 3.10
Table 3.11
Chapter 4
Table 4.1
Table 4.2
Chapter 5
Table 5.1
Table 5.2
Table 5.3
Table 5.4
Chapter 6
Table 6.1
Table 6.2
Table 6.3
Table 6.4
Chapter 8
Table 8.1
Table 8.2
Table 8.3
Table 8.4
Table 8.5
Chapter 9
Table 9.1
Chapter 10
Table 10.1
Table 10.2
Table 10.3
Table 10.4
Table 10.5
Table 10.6
Table 10.7
Table 10.8
Chapter 11
Table 11.1
Table 11.2
Table 11.3
Table 11.4
Table 11.5
Table 11.6
Table 11.7
Table 11.8
Chapter 12