Energy-efficient Analog Sensing for Large-scale, High-density Persistent Wireless Monitoring

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by  Vidyasagar Sadhu

Energy-efficient Analog Sensing for Large-scale,
High-density Persistent Wireless Monitoring
Vidyasagar Sadhu, Xueyuan Zhao, and Dario Pompili
Department of Electrical and Computer Engineering, Rutgers University–New Brunswick, NJ, USA
E-mails: xueyuan [email protected], [email protected], [email protected]
Abstract—The research challenge of current Wireless Sensor ment but also carry out digital communications and compu-
Networks (WSNs) is to design energy-efficient, low-cost, high- tations, both of which also require high bit resolution for
accuracy, self-healing, and scalable systems for applications
high precision and dynamic range. Digital motes as a result
7 such as environmental monitoring. Traditional WSNs consist
tend to be power hungry. On the other hand, sensing and
1 of low density, power-hungry digital motes that are expensive
0 and cannot remain functional for long periods on a single basic communications can be carried out by power-efficient
2 charge.Inordertoaddressthesechallenges,adumb-sensingand analog sensors. Moreover, the spatio-temporal characteristics
smart-processingarchitecturethatsplitssensingandcomputation of the underlying phenomenon being monitored by a Cyber
n
capabilities among tiers is proposed. Tier-1 consists of dumb
PhysicalSystem(CPS)areseldom,ifever,knowninadvance.
a sensors that only sense and transmit, while the nodes in Tier-2
J In order to support low-cost, high-confidence, and scalable
do all the smart processing on Tier-1 sensor data. A low-power
9 andlow-costsolutionforTier-1sensorshasbeenproposedusing CPS’s,therefore,itisdesiredthattoday’sdigitalsensormotes
1 AnalogJointSourceChannelCoding(AJSCC).Ananalogcircuit adapt their temporal resolutions and bit precisions during the
that realizes the rectangular type of AJSCC has been proposed operation of the WSN. However, the reality is that state-of-

] andrealizedonaPrintedCircuitBoardforfeasibilityanalysis.A the-art motes are “monolithic” due to various cost and design
I prototypeconsistingofthreeTier-1sensors(sensingtemperature
N considerations. Consequently, a careful and often irreversible
andhumidity)communicatingtoaTier-2ClusterHeadhasbeen
. demonstratedtoverifytheproposedapproach.Resultsshowthat choice of design parameters for digital motes is made prior
s our framework is indeed feasible to support large scale high to the WSN deployment, resulting in either over- or under-
c
[ density and persistent WSN deployment. provisioning: the former leads to heavy under-utilization of
IndexTerms—Three-tierArchitecture,SensorNetworks,Ana- motes, while the latter results in low sensing resolution and
1 log Joint Source Channel Coding, Shannon Mapping, Wireless
accuracy. Due to the cost of digital sensors, it would not
v Communications, Prototype, Measurement
be feasible to deploy thousands of such sensors to monitor
9
the environment. Hence, these questions are raised: can we
9 I. INTRODUCTION
5 have a low-cost and low-power solution for the sensing, and
5 Overview: The research and engineering objective of con- meanwhile being able to compress the sensing source and
0 tinuous monitoring of the physical world through minuscule performcodingtocombatagainstthedistortioninthewireless
. “smartdust”motesinthe‘90shelpedspurnearlytwodecades channel?
1
0 of exciting research in Wireless Sensor Networks (WSNs). Our Vision: To address these questions, we propose a
7 Some of that research has been successfully commercialized, modularized sensing architecture (Fig. 1) that represents a
1 while some other has been a precursor to recent advances paradigm shift from the traditional two-tier WSN architecture
: in the “Internet of Things.” Still, the vision of a large-scale (with monolithic sensing and computing digital motes report-
v
i WSNcomprisingtensofsensorspersquaremeterwhilebeing ingtoa“sink”)toathree-tierarchitecture.Inthisarchitecture,
X
robusttosensing/communication/computationfailuresremains while the “sink” tier—consisting of powerful fusion center(s)
r far from a reality. Indeed, even though Hewlett-Packard’s to perform central processing and higher control—still exists,
a
much touted Central Nervous System for the Earth project we split the traditional “digital motes” tier into two tiers
hopes to deploy billions of sensors all over the planet [1], its consisting of low-cost, energy-efficient, analog sensors at tier-
firstcommercialpartnershipwithShellforseismicmonitoring 1 (to support the sensing and communication functionalities)
still relies on motes that require VHS-sized enclosures [2]. and resource-rich digital cluster head nodes at tier-2 (to
The fundamental reason for this large gap between vision support processing and control). Our architecture uses a large
and reality of WSNs is that the design and production of number of low-cost/low-power/low-accuracy analog sensors
motes combining sensing, communication, and computation (≈130µWwithout radio power,$5)insteadofasmallnumber
capabilities into a single, miniature platform (the cornerstone of high-cost/power-hungry/high-accuracy digital motes. The
oftraditionalWSNparadigm)thatcanremainoperationalfor low-cost factor enables us to deploy these sensors in large
months, if not years, on a single charge, that can self heal scale and high-density thereby providing high spatial accu-
from internal failures, and that are still cheap is an extremely racy.Thelow-powerontheotherhandmeansthesensorsneed
difficult engineering challenge. not be put to sleep thereby providing high temporal accuracy
Motivation: Nowadays motes are composed of digital unlikethecurrentdigitalnodeswhichgotosleepoccasionally
processors,multipleAnalog-to-DigitalConverters(ADCs)and to conserve power. These vast number of analog sensors at
wireless transceivers. These digital motes sense the environ- tier-1 do only task of sensing and transmitting (which we
call dumb-sensing), while the onus of processing (which we Fusion Center (Tier 3)
call smart-processing) this sensor data for extracting useful
information lies on powerful digital nodes at tier-2. This
papermainlyfocusesonrealizingthislow-costandlow-power Digital Cluster Heads (Tier 2)
analogsensingattier-1.Forthis,wedesignsensornodeswith
Shannon-mapping capabilities. The Shannon mapping [21] is
Digital
a low-complexity technique for Analog Joint Source-Channel Comm.
Coding (AJSCC) [14]; it can compress two or more signals
Analog Sensor Nodes (Tier 1)
into one (introducing controlled distortion) while also staying
resilient to wireless channel impairments. We have currently Infrastructure monitoring Precise Agriculture Body Area Nets
used Frequency Modulation (FM), for the sensors to commu-
nicate to a digital cluster head in tier-2, due to its impressive
performance under low SNR conditions.
Our Contributions can be summarized as follows:
• Weproposeadumb-sensingandsmart-processingframe-
work for wireless sensor networks that splits sensing
and computational tasks between energy-efficient low Fig. 1: Tier-1 analog sensor nodes perform sensing and com-
cost sensors (Tier-1) and powerful digital nodes (Tier-2) municate with a digital Cluster Head (CH) via Analog Joint
respectively. We focus mainly on Tier-1 analog sensing
Source-ChannelCoding.Tier-2digitalCHsperformcomputa-
in this paper.
tion/processingandcontrol,anddigitallycommunicateamong
• We propose to use Analog Joint Source-Channel Cod- themselves and with the Tier-3 fusion center.
ing(AJSCC)forTier1torealizelowcostandlow-power
consumption;
• We verify the feasibility of our proposal through sim- with high-rate, high-resolution Analog to Digital Convert-
ulations and experiments using simple tier-1 prototype ers (ADCs) and digital transceivers to communicate with
developed by us. neighboring CHs, and processors to run fault-detection/data-
Paper Outline: The remainder of this paper is structured fusion algorithms (“Smart Processing”). Finally, data pro-
as follows. In Sect. II, we present our three-tier architecture cessed by the CHs will be retrieved through the fusion center
for WSNs and discuss its features. In Sect. III, we discuss (e.g., a mobile node such as a drone)—which may not be
our solution to low-power and low-cost tier-1 sensing using always connected to the network—that reconstructs the phe-
AJSCCanditsparameteroptimization.InSect.IV,wediscuss nomenon of interest and also possibly generates control com-
the hardware prototype developed and present some system- mands to support “closed-loop scenarios”. Our architecture
levelresultstostudythefeasibilityofourproposal.Finally,in willhelptosimultaneouslyimprovesensingresolution(spatial
Sect. V, we conclude the paper and discuss our future work. andtemporal),accuracy,andenergyefficiency.Smartprocess-
ing techniques at tier-2 consist of detecting faulty sensors,
II. THREE-TIERLOW-POWERSENSINGARCHITECTURE denoising, filtering, encryption (if needed), compression and
other techniques needed to process “big-data” coming from
Our architecture breaks away from the past design goal
tier-1sensors.Developingthesedataprocessing/computational
of homogeneous WSNs comprising high-power, resource-rich
techniques for tier-2 CHs will be considered as future work
digital motes with integrated sensing, communication, and
and outside the scope of this paper.
computation capabilities. Instead, we advocate a three-tier
architecture (Fig. 1) that corresponds to a high density of Upgrades to the sensing tier (Tier 1, composed of analog
extremely low-cost and low-power “dumb” analog sensors sensors) can be made independently without affecting the
with limited communication capabilities in Tier-1 and a low computing tier (Tier 2, composed of digital CHs), and vice-
densityof“smart”digitalClusterHeads(CHs)withadvanced versa. This is possible because the sensors only sense and
communication and computation capabilities in Tier-2. Tier-3 do not have any intelligence. So it should be easy to replace
consistsofafusioncenter(canbeaserveroramobiledrone) them with other sensors. Similarly, upgrades to the comput-
having similar functionalities of a Tier-2 sink in traditional ing capabilities of the CHs can be made without affecting
WSN architecture. While the communication among digital the analog sensors. Three-tier architecture also makes the
CHs in tier-2 can be digital, that between tier-2 and tier-3 WSNs incrementally deployable: any WSN following this
can be delay tolerant as the fusion center may not be always new paradigm can easily coexist (backward compatible) with
available. We would like to clarify that the general idea of already deployed WSNs in existing CPS’s. In a world of
tiered architectures for WSNs is not new to the research incrementaldeployment,webelievethismarksamajorcontri-
community; see, e.g., [20], [25], [27]. The main idea of this bution towards low-cost, high-confidence, scalable CPS’s. We
paper lies in its use of dumb all-analog sensors for low- claim that the broader applications of our proposed architec-
power sensing and communication at Tier 1 which should, in ture include low-cost, high-confidence monitoring for urban
principle,enablelarge-scale,high-densitywirelessmonitoring. infrastructure, precision agriculture, intelligent transportation
systems, and military surveillance, to name a few.
Signals from multiple analog sensors will be multiplexed
and detected at the digital CHs, which will be equipped In agreement with the Latin phase, Natura non facit saltus
errors along the parallel lines (or the spiral curve). Joint
analog source-channel coding achieves optimal performance
in rate-distortion ratio. It is known that to achieve optimal
performance in communications using separate source and
channel coding, complex encoding/decoding and long-block
length codes (which cause significant delays) are required.
It is worth noting that there are information-theoretic anal-
yses on whether the separate source-channel coding deployed
in real communication systems is optimal or not. Nazer and
Gastpar[16]arguethat,foraGaussiansensornetwork,analog-
scaled transmission performs exponentially better than a sep-
arate source-channel coding system. In [13], a sensing system
is studied for single memoryless Gaussian source, multiple
independent sensors with Gaussian noise, and a cluster head
node with standard Gaussian multiple-access channel. It is
statedthattheoptimalcommunicationstrategyisanalogscaled
transmission, where each sensor transmits a scaled signal
of the noisy sensed signal to the communication channel
Fig. 2: Shannon’s Rectangular Mapping. Sensed point is
connecting sensor nodes with the cluster head node. Also,
mapped to a point closest on the rectangular curve and the
analog communications can be optimal in certain circum-
length of the curve from origin to the mapped point (bold
stances, e.g., when Gaussian samples are transmitted over
part) is transmitted instead of two sensed values. Odd level
an Additive White Gaussian Noise (AWGN) channel and the
voltages are generated using Type-1 VCVS while that of even
sourceismatchedtothechannel.Asmentionedearlier,AJSCC
level are generated using Type-2 VCVS.
is resilient to channel noise because the channel noise only
introduces errors along the spiral curve or the parallel lines.
In contrast, linear mapping techniques such as Quadrature
(“nature does not make jumps”), our sensors are analog, as
Amplitude Modulation (QAM) have errors spread on the
measurements are taken for the real world, which is inher-
constellation plane. Therefore channel noise has less effects
entlyanalog.ComparedtoCommercialOff-The-Shelf(COTS)
on the error performance for Shannon mapping than linear
motes, the energy consumption of pure analog sensing can be
modulation schemes.
much lower: an all-analog node should consume, in theory,
All these reasons motivated us to choose the combination
on the order of mW or less power (which is comparable
of analog communication and Joint Source-Channel Cod-
to the power that can be harvested using, for example, a
ing (JSCC), hence AJSCC, as sensing/transmission scheme
compactsolarpanel),whileaCOTSnodespowerconsumption
for our low-cost, low-power Tier-1 analog sensors. AJSCC
is typically on the order of several tens of mW. Considering
performs analog compression at the symbol level. Also, the
the sensors’ low-power and low-cost benefits these can be
fact that symbols are memoryless makes it a low-latency and
either rechargeable or disposable. Broader applications of
low-complexity solution that is very suitable for practical
our approach include low-cost, high-confidence monitoring
implementations. Last, but not least, AJSCC schemes can
for intelligent transportation systems, military surveillance,
also achieve performance close to the Optimal Performance
urbaninfrastructure,precisionagriculture,andevenbodyarea
Theoretical Achievable (OPTA) for Gaussian sources [10],
networks (with no fusion center). We believe it will provide
[15], thus making it very attractive for our Tier-1 sensing.
significantbenefitsintermsofeaseofupgradeandscalingout
AJSCC requires simple compression and coding, and low-
of WSNs in addition to adaptive sensing resolution, accuracy,
complexity decoding. To compress the source signals (“sens-
and energy efficiency.
ing source point”), the point on the space-filling curve with
III. LOW-POWERTIER-1SENSING minimum Euclidean distance from the source point is found
We first discuss the reasons for choosing AJSCC by giving (“AJSCC mapped point”), as in Fig. 2. The two most-widely
an overview of the potential advantages of AJSCC. Then, we adopted mapping methods are rectangular (Fig. 2) and spiral
introduce our proposed circuitry for realizing AJSCC. shaped: in the former, the transmitted signal is the “accumu-
latedlength”of thelinesfromtheorigin tothemappedpoint;
A. Analog Joint Source Channel Coding (AJSCC) in WSNs
while in the latter it is the “angle” that uniquely identifies
AJSCC adopts Shannon mapping as its encoding the mapped point on the spiral. At the receiver (a CH), the
method [11], [14]. Such mapping, in which the design of reverse mapping is performed on the received signal using
rectangular (parallel) lines can be used for 2:1 compression MaximumLikelihood(ML)decoding.Theerrorintroducedby
(Fig. 2), was first introduced by Shannon in his seminal the two mappings is controlled by the spacing ∆ between
H
1949 paper [21]. Later work has extended this mapping to lines and spacing ∆ between spiral arms, respectively: with
S
a spiral type as well as to N:1 mapping [9]. The Shannon smaller∆ (or∆ ),approximationnoiseisreduced;however,
H S
mapping has the two-fold property of (1) compressing the channel noise is increased as a little variation can push the
sources (by means of N:1 mapping) and (2) being robust to received symbol to the next parallel line (or spiral arm).
(wireless) channel distortions as the noise only introduces In addition, the mapping signal range would also increase,
TABLE I: Relationship to prior work.
Related Description Comparisonwiththeproposedresearch
work
Patent[22] DigitalvideotransmissionbyAJSCC/Shannonmapping DigitalimplementationofAJSCC
Patent[17] Wirelessanalogsensorsforimplantationapplication Nosourceandchannelcodingconsidered
Paper[12] Software-definedradiosystemforAJSCCinindoorchannel DigitalimplementationofAJSCC
Paper[19] DigitalopticalcommunicationsystemwithAJSCCencodingforimage DigitalimplementationofAJSCC
transmission
Product[7] WSN340:ActiveMCUpowerconsumption:1.1mW Ourproposedsensorwillconsume≈130µWwithstate-of-the-artlow-
Product[18] MantaroCoSeN:ActiveMCUpowerconsumption:2.4mW powercomponents(OpAmps,etc.)[28].Thereispotentialtoreducethis
Product[6] TelosRevB:ActiveMCUpowerconsumption:6mW evenfurther(<50µW)whenallthefunctionalitiesareintegratedinto
Product[5] MICA2:ActiveMCUpowerconsumption:26.4mW amonolithiccomponentusinganalogICdesign.
pushing more resources for transmission. it back to 2D information using simple modulus calculation.
Thenumberoflevels,theencodedlengthandthequantization
B. Proposed Circuit Realization of AJSCC
error in V are determined by resolution sought in V (∆ ).
H H H
A low-power, low-cost, and high-accuracy analog circuit
To the best of our knowledge, there has been no prior work
needs to be designed as existing AJSCC-hardware solutions
onhowtorealizethislengthinpracticeusinganalogcircuitry.
are all digital and power hungry as they combine both sens-
We have come up with an innovative solution to calculate
ing/communicationandprocessingperthetraditionalarchitec-
the length of this curve as a function of the mapped V and
ture. For example, a Software-Defined Radio (SDR) system T
V values. Let’s assume the mapped point lies on level 1.
to realize AJSCC mapping has been reported in [12]. The H
In this case the encoded length varies proportional to V .
mapping was also recently implemented in an optical digital T
When the mapped point lies on level 2 it varies inversely
communication system in [19] and has been combined with
proportional to V (if the level 1 length is subtracted from
CompressiveSensing(CS)in[8]toimproverobustnessagainst T
it). In fact, this basic behavior can be observed at all odd
channelnoise.Shannonmappingencodingwasadoptedin[22]
and even levels respectively (i.e., assuming the total length of
foradigitalvideotransmission.Allthesedesignsolutionsuse
levels below it are subtracted from the encoded length). If we
digital microcontrollers, which are quite power hungry: for
consider the mapped point lying on some arbitrary level, the
example in [23], with a 1.8 V supply, the power consumption
encoded length would be equal to the sum of lengths of all
of a microcontroller alone can be as high as 450 mW
levels below it and the length either proportional (odd level)
(250 mA×1.8 V); not to mention that the actual power con-
or inversely proportional (even level) to V . This means there
sumed will be even greater when one considers other power- T
are two components that determine the encoded length - the
hungry digital components such as ADC/DAC/FPGA/DSP.
level on which the mapped point lies and whether the level is
Table I compares our work with the existing patents, papers
odd or even. The latter is easily found if we assign odd and
and products which are close to our work. To the best of our
even indicators to all levels which is trivial when we know
knowledge, none of them implemented Analog Joint Source
the number of levels (i.e., ∆ ) in advance and we make this
Channel Coding using analog circuitry to achieve low-power, H
assumptionasofnow.Theformercanbefoundbycomparing
low-costsensingaswedid.Whilecomparingourproductwith
V with threshold voltages of the levels (dashed lines in
theTIsensorin[19],weunderstandthattheTIsensorisdoing H
Fig.2).Henceeachlevelcontributesoneofthesethreevalues
many other processing jobs apart from just sensing, justifying
to the total encoded length: zero, partial (how much is based
it’s cost and power consumption. However, it is to be noted
onwhetheroddorevenlevel)andfulllevellength.Usingthis
that one of our main ideas in this paper is to deviate from
idea we came up with a circuit realization for each level. For
sucharchitecture,i.e.,tosplitthetwofunctionalities-sensing
the partial length case to realize proportionality, we made use
in tier-1 and processing in tier-2. We have also successfully
ofaVoltageControlledVoltageSource(VCVS)whichoutputs
demonstrated a working prototype using that architecture.
voltage that is proportional to the input voltage. Let’s call this
Because of this, our sensors that are to be deployed on the
Type-1 VCVS and for odd levels this can be used directly.
field become less expensive and less power-hungry lending
However for even levels, we need another type of VCVS, we
themselves well to high-density deployment which in turn
call it Type-2 VCVS that gives output inversely proportional
leads to highly accurate spatial and temporal sensing of the
to the input. For these reasons, we use odd (even) level and
environment.
Type-1(Type-2)levelinterchangeably.Wesometimesreferthe
Figure 2 shows the Shannon’s rectangular mapping curve
combinationoftwoconsecutivelevels(Type-1andType-2)as
applied to the range of temperature voltage, V and humidity
T a single stage.
voltage V . Let’s denote the cross point as the actual sensed
H
point. As Shannon Mapping maps the actual sensed point to With this information we can have the following circuit
the closest point on the rectangular curve, the circle denotes for each level to determine its contribution to the encoded
the mapped point. Hence 2D information consisting of V length/voltage. Fig. 3 shows the proposed circuit realization
T
and V has been compressed to 1D information, the length forlevel1andlevel2(stage1).Wecanhaveananalogmulti-
H
of the curve from the origin to the mapped albeit with some plexerthattakes0,V andType (foroddlevel)/Type
R 1,out 2,out
quantization error. This length of the curve can henceforth (for even level) as inputs and outputs one of these values
be used for modulation and transmission instead of V and based on it’s select signals. Here V , the saturation voltage
T R
V . The receiver upon receiving this 1D information decodes correspondstothevoltagethatisproportionaltothefulllength
H
Fig. 3: Proposed Analog Circuit for Shannon’s Rectangular
Mapping (only one stage is shown). V in comparison with
H
threshold voltages generates select signals for the two analog
Fig. 4: Signal chain block diagram. AJSCC voltage is FM
multiplexers to decide which of the three inputs goes to the
modulated and transmitted in the tier-1 sensor. Received
output. The outputs of both muxes are added to give this
baseband signal in tier-2 digital CH is sampled using ADC
stage output. Similar outputs from higher stages are added
to find peak frequency using FFT. Peak frequency is mapped
to give AJSCC encoded voltage which is FM modulated and
backtoAJSCCvoltagewhichisthendecodedtosensorvalues.
the mixed with semiorthogonal codes before RF transmission.
We have an assumption that the encoded signal has an
of the level. The select signals are generated by comparing
amplitudeconstraintD .ThisisbecausetheFMmodulator
V with threshold voltages of the levels. Finally the voltage max
H canonlyacceptasignalwithincertainamplitude.Ifwedenote
contributions from all levels are added to give the AJSCC en-
the number of levels by L, this constraint can be denoted by
coded voltage which is then modulated by frequency position
V L ≤ D . The extreme case will be V L = D where
modulation, and sent to RF module for transmission. 1 max 1 max
V L is the maximum output signal of AJSCC encoder. Due
It can be seen that our sensor node will be composed of 1
to this constraint, if we increase the parameter L, the voltage
low-cost mapping circuits, FM modulation circuits, and RF
V =D /L for x will be reduced. V is a constant value,
circuits.Nomicrocontrollerisneeded,andnoFPGAandDSP 1 max 1 2
and the line spacing ∆=V /(L−1).
chips are needed either. Hence, the total power consumption 2
TheAJSCCencodinganddecodingbytherectangularcurve
ofourdesigncouldbemuchlowerthanthatofpresentdigital
is depicted in Fig. 4. The output of the AJSCC circuit is
sensornodes,andthefabricationcostwillalsobemuchlower
first frequency modulated and is then sent to RF circuitry
iffabricatedonanIntegratedCircuit(IC).Alow-cost,compact
for wireless transmission over a noisy wireless channel. At
energy-harvesting unit for powering the sensor system can be
receiver, the baseband signal from RF is sampled by ADC
used, e.g., a tiny solar cell—given the sensor scale of a few
and is sent to FFT block for frequency peak detection. Once
cm2—thatcanprovidemW-levelpowersupplythusextending
the base-band frequency is determined, the AJSCC decoder
its lifetime to years. For more details about our prototype all-
finds the corresponding AJSCC voltage and then decodes it
analog tier-1 sensor, including Spice, breadboard and Printed
back to give reverse mapped signals xˆ and xˆ .
CircuitBoard(PCB)implementationandexperimentalresults, 1 2
Wehaveaninterestingtradeoffbehaviorhere.Withincreas-
please see [28].
ing L, the MSE of x drops as the spacing between the lines
2
(∆)reduces.However,duetotheconstraintofthetransmitted
C. AJSCC Parameter Optimization
signal, the voltage representing x will be smaller which will
1
In this section, we theoretically analyze the AJSCC system introduce higher error in MSE for x . With decreasing L, the
1
toderiveatoptimumparameters(numberoflevelsorthespac- quantization error in x increases leading to high MSE for
2
ing ∆ between parallel lines). Let us assume two independent x d. This tradeoff behavior has been studied via MATLAB
2
sources, X1 and X2, whose distribution is unknown. The two simulations to find an optimal L. We assumed two sources
sources are sensed and converted to voltages by the sensing withuniformdistributionbetween[0,1].TheparameterD
max
units. Let’s denote the two sensed signals by x1 and x2 and is set to 5. The signal Vd generated by AJSCC mapping is
assume their ranges are [0,V1], and [0,V2] respectively. The FM modulated, in which a scaling factor is applied to convert
AJSCC circuit with spacing ∆ between parallel lines outputs voltage to frequency. Assuming linear transformation from
the voltage Vd given by, voltage to frequency, and a scaling factor of 1000, the fre-
(cid:26) quencyrangeisfrom0Hzto5kHz.TheSNRinthesimulation
kV +x k iseven
V = 1 1 (1) is defined as the transmitted signal power to the noise power
d kV +V −x1 k isodd
1 1 in the channel. The transmitted signal power is assumed to
where the parameter k =floor(x2) be unity for FM modulation of continuous cosine wave of
∆
10−1
Sum MSE of [x x]
1 2
10−2 MSE of x1
MSE of x
2
E)10−3
S
M
Error (10−4
e
uar10−5
q
S
n
Mea10−6
10−7
10−8
0 50 100 150 200
Parameter L, maximum number of parallel lines
Fig. 5: MSE vs. parameter L, for SNR = −20 dB; Observed
optimum L is about 73.
Fig. 6: Prototype: 3 Tier-1 sensors (right bottom) communi-
cating to a Tier-2 receiver CH (left bottom). The baseband
amplitude equals to 1. The noise power is defined by the signals of all three channels are captured using NI Digital
variance of the Gaussian noise. It is assumed that the channel Acquisition System and processed/decoded on host computer
is static channel between the sensor to the cluster head. Since using LabView/MATLAB.
there is no sensor movement and the environment is also
static, it can be assumed that the channel gain is a constant
value with phase shift. In the receiver, the ADC samples at a
frequency of 65.536kHz and the frequency resolution of the 24
signal is assumed as 1Hz giving FFT size as 65536. Once the
22
peakfrequencyisdetermined,theAJSCCdecoderdecodesthe
baseband signal by first reverse mapping the frequency back 20
to voltage and then voltage back to xˆ and xˆ . Fig. 5 shows
1 2
18
the MSE-vs-L tradeoff behavior for an SNR value of -20 dB.
B)
We have observed that this FM modulated system achieves R(d16
a low sum MSE of 3∗10−4, but requires large number of SD
14
parallel lines, around 73, to achieve this minimum MSE. The
minimum sum MSE and the corresponding L doesn’t change 12
much for SNRs of −20dB, −10dB and 0dB. The mapping
1Tx -> dig CH
can be extended to more than two sources. In three sources 10 2Tx -> dig CH
3Tx -> dig CH
case,twosourceswillbediscrete,andonewillbecontinuous. 8
15 20 25 30 35 40 45
Twomoduluscalculationsneedtobeperformedatthereceiver
CSNR(dB)
for three source scenario. The above simulated system can
be generalized to a sensor network, where different sensors Fig.8:MeasuredSDR-vs-CSNRperformanceforone,twoand
transmit the FM modulated signal in overlapped frequency three Tier-1 sensors communicating with a Tier-2 CH. Due to
bands. The sensor signals are separated by semi-orthogonal receiver diversity, SDR of two and three sensor cases is high
signals mixed with the transmitted signal. In receiver, there
comparedtoonesensorcase.Duetoreducedperformance,the
will be interference from other sensors, thus the SNR will be
one-sensor case exhibits a sharp decline in SDR value. The
SINR (Signal to Interference-plus-Noise Ratio). The level of
observed step is because the decoded V values are discrete
H
interference is determined by the semi-orthogonal signals.
IV. PERFORMANCEEVALUATION entirelydesignedbyus(seeFig.6).Thistier-1sensorconsists
We first describe the Printed Circuit Board (PCB) tier-1 of three major blocks - AJSCC encoding block, DC-to-sine
sensorwedevelopedalongwithpowerandcostanalysis.Later wave conversion circuit and an RFIC module. The AJSCC
we present some performance results of our Tier-1 sensor encoding block takes temperature and humidity voltages as
prototypewhenone,twoandthreeofthemcommunicatewith input and outputs the AJSCC encoded voltage. It implements
a simple tier-2 receiver using FDMA. 11 VCVS levels in total as per the setup described above
Printed Circuit Board Sensor: We first tested our circuit (∆ = 0.3V). It also has option to take input from two
H
idea (presented in Sect. III-B) on breadboard and obtained external sources for testing and verification purposes. Then,
satisfactory results. This motivated us to go a step further to a sine wave whose frequency is proportional to the AJSCC
implement the full circuit (all stages) along with the RF part voltage is generated using a COTS timer chip. This sine wave
(as a COTS component) i.e., a full-fledged sensor on a PCB is given as input to the COTS RF module which frequency
45 35 38
true SDR VT true SDR VT true SDR VT
40 ftirtuteed S SDDRR V VHT ftirtuteed S SDDRR V VHT 36 ftirtuteed S SDDRR V VHT
35 ftirtuteed S SDDRR S VUHM ftirtuteed S SDDRR S VUHM 34 ftirtuteed S SDDRR S VUHM
fitted SDR SUM fitted SDR SUM fitted SDR SUM
30 32
30
R(dB)25 R(dB) R(dB)30
SD SD SD28
20
25 26
15 24
10 22
5 20 20
32 34 36 38 40 42 44 24 26 28 30 32 34 36 38 40 42 15 20 25 30 35 40
CSNR(dB) CSNR(dB) CSNR(dB)
(a) (b) (c)
Fig.7:SDR-vs-CSNRperformancefordifferentnumberoftier-1sensorscommunicatingtoadigitalclusterheadusingdifferent
channels: (a)1 sensor (b) 2 sensors (c) 3 sensors. Note the large jumps in SDR (seen in (a)) owing to similar behavior in SDR
of V which is because of the discreteness in Vˆ
H H
modulates it and transmits the modulated signal at 2.4 GHz consuming about 10 nW can be used for our circuit resulting
ISM band. FM requirement is to be noted here as we have in a power consumption of ≈130µW. We are also optimistic
shown in Sect. III-C that it has robust performance even at that the sensor cost would reduce to less than $5 leveraging
low SNR conditions. economies of scale via mass production using the latest IC
Sensing Power and Cost Estimation: We analyze the power technology.Achievingbothgoalswillenablecriticalfuturistic
consumption of this tier-1 analog sensor by comparing it applications such as persistent wireless sensing and IoT-based
with that of existing sensors. State-of-the-art sensor nodes solutions.
consume ≈ 0.5 mA in active mode and a few µA in sleep Prototype Performance: We have developed a simple
mode with supply voltages in the range 1.8 − 3.0 V, i.e., prototype (Fig. 6) consisting of three tier-1 sensors commu-
0.9−1.5mWwithouttakingintoaccounttheradiopower:the nicating to a simple tier-2 Cluster Head (CH). The receiver
activepowerconsumptionismainlyduetothemicrocontroller CH, also designed by us, has three antennas for receiving the
andAnalog-to-Digital(A/D)conversions([4],[18]).Wehave signals of the three sensors. There are three RF receivers to
listedsomeofthewell-knownwirelesssensornodeswiththeir downconvert the RF signals received by the three antennas.
active MCU current consumption in Table. I for comparison. The baseband signals at the output of RF receivers (which
In contrast, our all-analog sensor does not use power-hungry are supposed to be sine waves as in the case of Tx) are
A/D’s or microcontrollers (MCUs). The current drawn by the then fed to NI Digital Acquisition (DAQ) system to detect
AJSCC baseband circuitry (using COTS OpAmps, Multiplex- their peak frequency in a LabView program. MATLAB is
ers, etc.), i.e., the entire board excluding the RFIC module, usedinsideLabViewtoperformspectralanalysisofthesignal
is ≈ 3 mA with a supply voltage of 5 V (equivalent to (such as SNR calculation) and also to map back the detected
≈15 mW); the cost of the AJSCC PCB is about $25. These peak frequency to DC voltage (AJSCC voltage) and then
numbers, which are high because of (a) the use of COTS decode the AJSCC voltage back to temperature and humidity
components and (b) duplication of hardware for each stage, voltages, [Vˆ ,Vˆ ]. Mean Square Error (MSE) and the Signal
T H
can be reduced drastically if Integrated Circuit (IC) design is to Distortion Ratio (SDR) has been calculated as follows.
adopted.Whileourimplementationservesasfeasibilitystudy,
MSE =(V −Vˆ )2+(V −Vˆ )2
webelievethepowerconsumptioncanbereducedto<50µW T T H H
1
if (1) our circuit is redesigned using the latest nm-technology SDR=10log ( )
components(forOpAmps,Comparators,andMultiplexers)(2) 10 MSE
ourcircuitisredesignedintegratingallthefunctionalityintoa We measured and compared the prototype’s performance
single Integrated Circuit (IC) rather than using discrete COTS for cases when one, two and three sensors are communicating
components (3) hardware duplication issue is solved and we simultaneously to digital CH using FDMA (different chan-
have some preliminary ideas too on that front (possibility of nels). Fig. 7(a), Fig. 7(b), Fig. 7(c) show the SDR-vs-CSNR
<10 µW) performance for these three cases respectively. Here CSNR
Let us provide a rough estimate using just (1) above: (Channel Signal-to-Noise Ratio) is the SNR of the baseband
our circuit in total (5 and half stages/11 levels) consists of signal at the output of receiver RF module. SDR and CSNR
16 OpAmps, 17 Comparators, and 11 Multiplexers, where values are plotted by varying the distance between Tx and
OpAmps are clearly the major contributors to the over- Rx and fixing V and V . We observe that at high CSNR,
T H
all power consumption. There are many low-power designs combinedSDRislimitedbythatofV .ThisisbecauseV is
H H
proposed for these components. For example, a low-power near the threshold voltage (rather than level voltage) resulting
OpAmp [26] consuming about 8 µW, a comparator [24] con- in large quantization error in V and so very less SDR. Also
H
sumingabout12.7nW,andananalogmultiplexer(ADG704) in (a), we see a step, this is because SDR of V is discrete.
H
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