Design of RSD-cyclic and hybrid RSD-Cyclic/sigma-delta ADCs

273 Pages·2007·8.38 MB·English

by  Youssef H. Atris

DESIGN OF RSD-CYCLIC AND HYBRID RSD-CYCLIC/SIGMA-DELTA ADCs

A Dissertation by
Youssef H. Atris
MSEE Electrical Engineering, Wichita State University, Wichita, Kansas, 1998
BS Physics, Friedrich Wilhelms Universität, Bonn, Germany, 1992

Submitted to the Department of Electrical and Computer Engineering
and the faculty of the Graduate School of
Wichita State University
in partial fulfillment of
the requirements for the degree of
Doctor of Philosophy

July 2007
© Copyright 2007 by Youssef H. Atris
All rights reserved
DESIGN OF RSD-CYCLIC AND HYBRID RSD-CYCLIC/SIGMA-DELTA ADCs

I have examined the final copy of this dissertation for form and content, and recommend that it
be accepted in partial fulfillment of the requirement for the degree of Doctor of philosophy with
a major in electrical engineering.

_____________________________________
Larry D. Paarmann, Committee Chair

We have read this Dissertation
and recommend its acceptance

_____________________________________
Edwin Sawan, Committee Member

_____________________________________
Hyuck Kwon, Committee Member

_____________________________________
John Watkins, Committee Member

_____________________________________
Zhiren Jin, Committee Member

Accepted for the College of Engineering

____________________________________
Zulma Toro-Ramos, Dean

Accepted for the Graduate School

____________________________________
Susan Kovar, Dean

iii
In memory of my beloved parents
Hussien and Sikna Atris
God bless their souls
iv
“Nichts ist rührender, als wenn eine Liebe, die sich im stillen genährt, eine Treue, die sich im
verborgenen befestigt hat, endlich dem, der ihrer bisher nicht wert gewesen, zur rechten Stunde
nahe kommt und ihm offenbar wird. Die lange und streng verschlossene Knospe war reif, und
Wilhelms Herz konnte nicht empfänglicher sein”

Johann Wolfgang Von Goethe, Wilhelm Meisters Lehrjahre

v
ACKNOWLEDGMENTS

Pursuing graduate research and having a full time engineering position has been a very
demanding task on me personally that has not just affected my own life, but also all the people
around me. Without the support of all these people and their understanding and support doing the
research and writing this dissertation would not have been possible.
I would like to start with my advisor Dr. Larry Paarmann. I would like to thank him for
his continued support through out the years and for his endless patience. Without his support and
advice this work would have not been possible. His guidance and insistence on certain issues
made me realize a lot of things that were not clear to me and improve my work. I am very
grateful to all his effort. I would like to thank him especially for his very thorough review of my
dissertation. This by itself has been a very time consuming task. His comments and suggestions
were very helpful and important to the final outcome of this research. I would also like to thank
all the committee members who served on my committee, Dr. Sawan, Dr. Kwon, Dr. Watkins
and Dr. Jin. I really appreciate all the advice and feedback I have received while writing this
®
dissertation. My special thank is to Freescale Semiconductor Inc., specifically the Radio
Product Divisions Design manager Babak Bastani for his support to do this work. I would like
also to thank my direct manager Mike Schulze who was flexible enough to allow me to modify
my work schedule to be able to work on this dissertation.
My wife Siham and my two sons, Ahmad and Hassan, deserve a lot of credit. Without
their love and understanding I would have not been able to accomplish this challenging task. I
hope I can make up for all the weekends and long nights that they had spent without me. To them
a special thank.
vi
ABSTRACT

In this research work two contributions to the area of analog to digital data converters
have been discussed. The area of focus is the RSD-Cyclic and sigma-delta ADC. First a novel
hybrid RSD-Cyclic-sigma-delta architecture is introduced which is a combination of the RSD-
Cyclic ADC and sigma-delta ADC architectures. The resolution obtained with this hybrid
architecture is n = n +n , where n1= MSB stands for the most significant bits obtained from
1 2 RSD
the RSD-architecture and n2= LSB stands for the least significant bits obtained from the
SDL
sigma-delta architecture. Since the sigma-delta block is required to achieve only an n2-bit
( )
resolution n2,n1< n the over-sampling ratio required for the sigma-delta is not as high as the
over-sampling ratio required to achieve n-bit resolution. Also the requirements on the RSD-
Cyclic block are only the requirements to achieve n1-bit resolution, which means that the
requirements on the analog building blocks for the RSD-Cyclic part are more relaxed. Secondly,
in the RSD-Cyclic area we have introduced a circuit technique that allows an entire ADC system
to run on one operational amplifier without any loss of functionality. Therefore we will be saving
power and area, both very desirable features for mobile applications.

vii
TABLE OF CONTENTS

Chapter Page
1. INTRODUCTION ……………………………………………………………...............1

1.1 Motivation………………………………………….…...….……………...............1
1.2 Research Contributions ………………………………….…...….……………...2
1.2.1 Literature on RSD-Cyclic Analog to Digital Converters………………….5
1.2.2 Literature on Sigma-Delta Analog to Digital Converters…………………6
1.2.3 Literature on Hybrid Analog to Digital Converters….……………………7
1.2.4 Placing the Hybrid Architecture in Its Application Space………………...8
1.3 Thesis Organization…….………...…………………………….…...….…………9

2. ANALOG TO DIGITAL CONVERTER BASICS……………………………………...11

2.1 Analog to Digital Conversion Terminology and Performance Metrics……….....11
2.1.1 Quantization……………………………………………………………...11
2.1.2 Quantization Errors………………………………………………………12
2.1.3 List of Commonly Used ADC Performance Metrics…………………….13
2.2 Survey of Different Analog to Digital Converter Topologies …………………..20
2.2.1 Nyquist-Rate Analog to Digital Converters……………………………...22
2.2.1.1 Single Slope Ramp-Integrating ADC……………………………22
2.2.1.2 Dual Slope Integrating ADC……………………………………..23
2.2.1.3 Charge Balancing Dual Slope ADC……………………………..25
2.2.1.4 Ramp Counter ADC……………………………………………...26
2.2.1.5 Tracking ADC……………………………………………………28
2.2.1.6 Flash ADC……………………………………………………….29
2.2.1.7 Multi-Step Parallel Flash ADC…………………………………..30
2.2.1.8 Successive Approximation ADC………………………………...31
2.2.1.9 Algorithmic ADC………………………………………………...32
2.2.1.10 Pipelined Successive Approximation ADC……………...33
2.2.1.11 V/F Charge Reset ADC………………………………….34
2.2.1.12 V/F Charge Balancing ADC……………………………..35
2.2.1.13 Charge Redistributing ADC……………………………..37
2.2.1.14 A 3- Bit Charge Redistributing ADC Example………….38
2.2.1.15 RSD-Cyclic ADC………………………………………...38
2.2.1.15.1 Basic RSD Algorithm……………………………………39
2.2.1.15.2 Single Ended Operation of RSD-Cyclic ADC…………...40
2.2.1.15.3 Single Ended RSD-Cyclic Example 1…………………...41
2.2.1.15.4 Single Ended RSD-Cyclic ADC Example 2……………..44
2.2.1.15.5 Differential Ended Operation of RSD-Cyclic ADC……..46
2.2.1.15.6 Differential Ended RSD-Cyclic Example 1……………...49
2.2.1.15.7 Differential Ended RSD-Cyclic Example 2……………...52
2.2.1.15.8 Possible RSD-Cyclic ADC Implementation……………..53
viii
TABLE OF CONTENTS (CONT)

Chapter Page
2.2.2 Noise Shaping Analog-to-Digital Converters……………………………57
2.2.2.1 Oversampling…………………………………………………….57
2.2.2.2 Δ-Modulation……………………………………………………60
2.2.2.3 ΣΔ-modulation…………………………………………………..62

3. RSD-CYCLIC ANALOG TO DIGITAL CONVERTER ANALYSIS AND
DESIGN………………………………………………………………………………….69

3.1 Capacitor Mismatch………………………………………...................................71
3.2 Finite Operational Amplifier Gain……………………………………………….72
3.3 Finite Settling Time of the Operational Amplifier……………………………....74
3.4 First Order Estimate Due to Cap-Mismatch, Op-amp Finite Gain and Settling
…………………….……………………………………………………………...75
3.5 Operation Amplifier Minimum Gain A Requirement………………………...77
min
3.6 Operational Amplifier Gain-Bandwidth Requirement…………………………...79
3.7 Operational Amplifier Slew Rate Requirement………………………………….80
3.8 Minimum Capacitor Size Requirement………………………………………….81
3.9 Capacitor Mismatch Requirement……………………………………………….83
3.10 RSD-Cyclic Design Parameter Example 1………………………………………85
3.11 RSD-Cyclic Design Parameter Example 2………………………………………86

4. NEW ONE OPERATIONAL AMPLIFIER ADC SYSTEM BASED ON RSD-CYCLIC
ANALOG TO DIGITAL CONVERTER ARCHITECTURE …………………………..88

4.1 Overview of the New One Operational Amplifier ADC System………………..88
4.2 One Operational Amplifier ADC System and Circuit Analysis…………………92
4.3 One Operational Amplifier ADC Circuit Implementation …………………... 103
4.4 One Operational Amplifier ADC System Simulation Results………………….124

nd
5. 2 -ORDER SIGMA-DELTA ANALOG TO DIGITAL CONVERTER ANALYSIS
AND CIRCUIT DESIGN………………………………………………………………131

nd
5.1 Simulation of the 2 -Order SDL………………………….................................139
nd
5.2 Non-Linearity in 2 -Order SDL………………………………………………..141
nd
5.3 Stability of the 2 -Order SDL…………………………….................................142
5.4 Dead-Band Behavior……………………………………………………………144
nd
5.5 Alternate 2 -order SDL Structures…………………….....................................144
nd
5.6 2 -Order SDL Design Example 1……………………………………………...146
nd
5.7 2 -Order SDL Design Example 2……………………………………………...155
ix
TABLE OF CONTENTS (CONT)

Chapter Page
6. NEW HYBRID ADC ARCHITECTURE 157

6.1 Overview of Proposed New Hybrid ADC Architecture………………………..157
6.1.1 Hybrid RSD-Cyclic-Sigma-Delta ADC Simplified Structure and
Operation………………………………………………………………..157
6.1.2 Possible Circuit Implementation………………………………………..160
6.1.3 n1-Bit RSD-Cyclic Block………………………………………………162
6.1.4 n1-Bit DAC……………………………………………………………..164
6.1.5 Difference/Gain/Anti-Alias Filter Circuit………………………………164
6.1.6 n2-Bit Sigma-Delta Circuit……………………………………………..166
6.1.7 Decoder Circuit…………………………………………………………166
6.2 Hybrid ADC Analysis…………………………………………………………..166
6.3 Hybrid ADC Circuit Implementation…………………………………..............173
6.3.1 Clocking Scheme……………………………………………………….173
6.3.2 Hybrid ADC Circuit Blocks……………………………………………176
6.4 Hybrid ADC Simulation Results……………………………………………….205
6.5 Comments on the Data and Design Guidelines for the Hybrid Architecture…..211

7. CONCLUSION ………………………………………………………………………...212

REFERENCES ……………..………………………………………………………………….213

APPENDICES ……………..………………………………………………………………….218

A. List of MATLAB® Programs…………………………………………………...219
B. MATLAB® Programs Code………….………………………….……………...221

x