Design of 28 nm FD-SOI CMOS 800 MS/s SAR ADC for wireless applications

130 Pages·2016·3.33 MB·English

Design of 28 nm FD-SOI CMOS
800 MS/s SAR ADC for wireless
applications
Master’s thesis in Embedded Electronic System Design
VICTOR ÅBERG
Department of Computer Science and Engineering
CHALMERS UNIVERSITY OF TECHNOLOGY
UNIVERSITY OF GOTHENBURG
Gothenburg, Sweden 2016
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Master’s thesis 2016
Design of 28nm FD-SOI CMOS 800MS/s SAR ADC for
wireless applications
VICTOR ÅBERG
Department of Computer Science and Engineering
Chalmers University of Technology
Gothenburg, Sweden 2015
Design of 28nm FD-SOI CMOS 800MS/s SAR ADC for wireless applications
VICTOR ÅBERG
© VICTOR ÅBERG, 2016.
Examiner: PER LARSSON-EDEFORS, Computer Science and Engineering
Supervisor: LARS SVENSSON, Computer Science and Engineering
Co-supervisor: CHRISTIAN FAGER, Microtechnology and Nanoscience
Master’s Thesis 2016
Department of Computer Science and Engineering
Chalmers University of Technology
SE-412 96 Gothenburg
Telephone [phone]
Typeset in LATEX
Department of Computer Science and Engineering
Gothenburg, Sweden 2016
iv
Abstract
As user expectations for higher bandwidth continue to rise, new techniques are required.
One such is the massive-Multiple Input Multiple Output (MIMO), building on dozens or
hundredsofantennasallhavingtheirownantenna. Makingcompact,lowcosttransceivers
then becomes essential. Silicon technology fulfils the cost while suffering in terms of
performance which needs to be compensated for by active pre-distortion which require an
Analog-to-Digital Converter (ADC). This converter must have low power consumption,
small footprint and achieve high sample rates in order to be useful.
This work tries to fulfil these demands by implementing a Successive-Approximation-
Register (SAR) Analog-to-Digital Converter (ADC) in a 28nm Fully Depleted Silicon on
Insulator (FD-SOI) Complementary Metal-Oxide Semiconductor (CMOS) process. The
converterhasbeenimplementedbasedontheprincipleofalternatingcomparatorsincom-
bination with a redundantly scaled Capacitive Digital-to-Analog Converter (CDAC) that
help increase the operation speed. The implementation also includes additional circuitry
in order to support testing of the circuit.
The implemented ADC shows an SNDR = 38.4dB at a sample rate of 800MS/s.
The converter consumes 1.1mW of power while doing this which results in a FoMW =
20.3fJ/conversionstep. This Figure of Merit (FoM) is among the lowest reported for high
speed ADC.
Keywords: SAR, ADC, Redundant scaling, Alternating comparator, 800MS/s
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Acknowledgement
Firstly, I would like to thank my supervisor Lars Svensson for his support during this
project, and the discussions which brought deeper insight into the work. Secondly, I
would like to thank my co-supervisor Christian Fager for the insights in the intended use
for the converter. I would also like to thank Erik Ryman for his help with getting started
with the 28nm process.
I would also like to thank the other students in the master thesis room for our inter-
esting conversations and the insight I gained about my work by discussing it with them.
Lastly, I would like to thank my family for their support during these five years of
studies with BSc and MSc.
Victor Åberg, Gothenburg, Sweden June 22, 2016
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Contents
List of Figures xiii
List of Tables xvi
Acronyms xx
1 Introduction 1
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Purpose and goal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Delimitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.4 Document structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Technical background 3
2.1 Fundamental properties of analog to digital conversion . . . . . . . . . . . . 3
2.1.1 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.2 Quantization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 ADC topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.1 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.2 Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.3 Successive-Approximation-Register . . . . . . . . . . . . . . . . . . . 11
2.2.4 Flash vs Pipeline vs SAR . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.5 Time Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Trends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Generic SAR topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.1 Track and Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.2 Sampling capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.3 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.4 SAR logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.5 Feedback reference voltage generator . . . . . . . . . . . . . . . . . . 17
2.5 State transition control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.5.1 Synchronous control . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.5.2 Asynchronous control . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.5.3 Metastability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6 Reference voltage scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6.1 Binary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.6.2 Redundant non-binary . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.6.3 Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.6.4 Binary vs Non-binary vs Compensation . . . . . . . . . . . . . . . . 24
2.7 Charge redistribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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Contents
2.8 Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.8.1 Offset voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.8.2 Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.9 Offset calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.9.1 Digital post processing . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.9.2 Capacitor switching . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.9.3 Body biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.9.4 Current injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.10 Kickback noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.10.1 Kickback noise reduction . . . . . . . . . . . . . . . . . . . . . . . . 32
2.11 Comparison measures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.11.1 Signal-to-Noise Ratio (SNR) . . . . . . . . . . . . . . . . . . . . . . 34
2.11.2 Signal-to-Noise-and-Distortion Ratio (SNDR) . . . . . . . . . . . . . 34
2.11.3 Spurious Free Dynamic Range (SFDR). . . . . . . . . . . . . . . . . 34
2.11.4 Differential non-linearity error (DNL) . . . . . . . . . . . . . . . . . 34
2.11.5 Integral non-linearity (INL) . . . . . . . . . . . . . . . . . . . . . . . 35
2.11.6 Walden Figure of Merit (FoMW) . . . . . . . . . . . . . . . . . . . . 36
2.11.7 Schreier Figure of Merit (FoMS) . . . . . . . . . . . . . . . . . . . . 37
2.12 Technology node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.13 Related works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3 Method 39
3.1 Methodologies used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.1.1 Literature study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.1.2 Design process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.1.3 Verification process . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2 Work flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.2.1 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.2.2 Circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.2.3 Circuit layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4 Specification 43
4.1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.2 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3 CDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5 Design 47
5.1 ADC topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.2 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.2.1 Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.2.2 Offset voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.2.3 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.2.4 Kickback noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.2.5 Kickback noise reduction . . . . . . . . . . . . . . . . . . . . . . . . 51
5.3 CDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.3.1 Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.3.2 Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.3.3 Sampling noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.3.4 Reference voltage adjustment . . . . . . . . . . . . . . . . . . . . . . 59
5.4 SAR logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
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