Table Of ContentCONTINUOUS-TIME DELTA-SIGMA
MODULATORS FOR
HIGH-SPEED A/D CONVERSION
Theory, Practice and Fundamental
Performance Limits
THE KLUWER INTERNATIONAL SERIES
IN ENGINEERING AND COMPUTER SCIENCE
ANALOG CIRCUITS AND SIGNAL PROCESSING
Consulting Editor:Mohammed Ismail. Ohio State University
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CONTINUOUS-TIME DELTA-SIGMA
MODULATORS FOR
HIGH-SPEED A/D CONVERSION
Theory, Practice and Fundamental
Performance Limits
by
James A. Cherry
Philsar Electronics, Inc
and
W. Martin Snelgrove
Philsar Electronics, Inc.
KLUWER ACADEMIC PUBLISHERS
NEW YORK,BOSTON , DORDRECHT, LONDON, MOSCOW
eBook ISBN 0-306-47052-7
Print ISBN 0-792-38625-6
©2002 Kluwer Academic Publishers
New York, Boston, Dordrecht, London, Moscow
All rights reserved
No part of this eBook may be reproduced or transmitted in any form or by any means, electronic,
mechanical, recording, or otherwise, without written consent from the Publisher
Created in the United States of America
Visit Kluwer Online at: http://www.kluweronline.com
and Kluwer's eBookstore at: http://www.ebooks.kluweronline.com
To Melissa
Contents
List of Figures xi
List of Tables xvii
List of Abbreviations and Symbols xix
Preface xxv
Acknowledgments xxix
1. ∆∑M CONCEPTS 1
1. A Brief Introduction to ∆∑M 1
1.1 Operating Principles 1
1.2 Design Choices 7
2. Why Continuous-Time ∆∑M? 11
3. Performance Measures 12
3.1 Power Spectrum Estimation 12
3.2 Signal to Noise Ratio (SNR) 15
3.3 Other Performance Measures 20
4. Simulation Methods 25
4.1 Discrete-Time Modulator Simulation 25
4.2 Continuous-Time Modulator Simulation 27
5. Summary 28
2. DESIGNING CT MODULATORS 29
1. Ideal ∆∑M Design 29
1.1 The Impulse-Invariant Transform 29
1.2 Exploiting the Equivalence 31
1.3 Band Pass Modulators 35
2. Implicit Antialias Filters 39
3. Unequal DAC Pulse Rise/Fall Time 45
4. Practical Design and Characterization 47
4.1 SPICE-Based Feedback Setting 47
4.2 SPICE Design Dual: z-Domain Extraction 50
5. Summary 58
3. ∆∑M IMPLEMENTATION ISSUES 59
vii
viii CONTINUOUS-TIME DELTA–SIGMA MODULATORS
1. Nonidealities in ∆ΣMs 59
1.1 Op Amps 59
1.2 Mismatch and Tolerance 62
1.3 Quantizers 64
1.4 Circuit Noise 65
1.5 Other Nonidealities 65
2. A Survey of Important CT ∆ΣM Papers 67
3. High-Speed CT ∆ΣM Performance 72
4. Summary 74
4. EXCESS LOOP DELAY 75
1. Effect of Excess Loop Delay 76
2. Double Integration Modulator 80
2.1 Root Locus 81
2.2 In-Band Noise 82
2.3 Maximum Stable Amplitude 84
2.4 Dynamic Range 85
3. f /4 Fourth-Order Band Pass Modulator 86
s
4. Higher-Order Modulators 86
5. Modulators with a Multibit Quantizer 93
6. Compensating for Excess Loop Delay 95
6.1 DAC Pulse Selection 95
6.2 Feedback Coefficient Tuning 96
6.3 Additional Feedback Parameters 101
7. Summary 103
5. JITTER AND METASTABILITY 105
1. Preliminaries 105
1.1 Jitter in CT Modulators 105
1.2 Modulator Architecture 106
1.3 Simulation Method 107
2. White Clock Jitter 108
2.1 LP Modulators with NRZ Feedback 108
2.2 Modulators with RZ and/or HRZ Feedback 113
3. Clocking with a VCO 116
3.1 Modeling VCO Phase Noise 118
3.2 Effect of Accumulated Jitter on Performance 119
4. Latches and Metastability 124
4.1 Digital Circuits vs. ∆ΣMs 125
4.2 Characterization Method for ∆ΣMs 127
4.3 Validation of Quantizer Model 128
5. Real Quantizer Performance Effects 133
6. Mitigating Metastability Performance Loss 141
6.1 Parameter Scaling 141
6.2 Regeneration Time 143
6.3 Preamplification 146
6.4 Additional Latching Stages 146
Contents ix
6.5 Other Modulator Architectures 153
7. Maximum Clocking Frequency 154
8. Summary 157
6. BP ∆ΣM DESIGN PROCEDURE 161
161
1. Design Problem Statement
2. Input Transconductor Gg1 162
3. Tank Components and Gq 166
4. Feedback DAC Currents and Gg2 167
5. Linearity of Internal Transconductors 167
6. Summary 172
7. A 4GHZ 4TH-ORDER BP ∆ΣM 175
1. Parameters for This Design 175
2 . Circuit Blocks 178
2.1 Resonator 178
2.2 Latch 190
2.3 Output Buffer 194
2.4 DAC 198
2.5 Complete Circuit 198
3 . Measurement Results 200
3.1 Resonator 205
3.2 Latch 210
3.3 Output Buffer 215
3.4 DAC 216
3.5 Dynamic Range 216
4 . Result Commentary 218
5. Summary 224
8. CONCLUSIONS 229
1. Summary of Results 229
2. Usefulness of High-Speed CT ∆ΣM 230
3. Future Work 232
List of Figures
1.1 Basic components of a ∆ΣM for ADC. 2
1.2 Linearizing the quantizer in a ∆ΣM. 2
1.3 STF(z) and NTF(z) for circuit of Example 1.1. 4
1.4 Simulated output bit stream power spectrum. 5
1.5 Complete ∆ΣM ADC block diagram including decimator. 6
1.6 General mth-order low pass ∆ΣM structure. 7
1.7 Typical radio receiver application for a band pass ∆ΣM. 9
1.8 A multistage ∆ΣM. 10
1.9a Effect of windowing on unwindowed output spectrum. 14
1.9b Effect of windowing on windowed output spectrum. 14
1.10 Effect of averaging on spectrum variance. 16
1.11 Unwindowed averaged periodogram near dc. 17
1.12a Hann-windowed averaged periodogram near dc. 19
1.12b Welch-windowed averaged periodogram near dc. 19
1.13a Dynamic range plot for ideal double integration ∆ΣM. 21
1.13b Improvement of double integration ∆ΣM SNR with
oversampling. 21
1.14a Ideal double integration ∆ΣM spectrum with –6dB input. 22
1.14b Ideal double integration ∆ΣM spectrum with –2dB input. 22
1.15 InP second-order CT ∆ΣM by Jensen et al. 24
1.16 A general DT ∆ΣM including input prefiltering. 25
2.1a Open loop CT ∆ΣM. 30
2.1b Open loop DT ∆ΣM. 30
2.2 Block diagram for LP CT ∆ΣM from Figure 1.15. 36
2.3 Block diagram for BP CT ∆ΣM with integrators re-
placed by resonators that cannot implement desired
equivalent H(z) . 37
2.4 Multi-feedback BP CT ∆ΣM architecture. 37
2.5 Common DAC pulse types. 38
xi
xii CONTINUOUS-TIME DELTA–SIGMA MODULATORS
2.6 ECL-style latched comparator with preamplification for
enhanced resolution at high speed. For an NRZ com-
parator, connect the final differential pair via the dashed
lines; for RZ, connect the dotted lines instead. 38
2.7 Matlab code for multi-feedback f /4 BP modulator. 40
s
2.8 First-order CT ∆ΣM. 42
2.9a Implicit antialias filters for various modulators. 44
2.9b Detail of implicit antialias filter plot. 44
2.10 Effect of unequal DAC pulse rise and fall times. 45
2.11 First-order modulator asymmetric DAC pulse: effect
for dc input of 0V (left) and overall transfer character-
istic (right). 46
2.12 RZ DAC pulses for circumventing asymmetry problems. 47
2.13a Starting position for SPICE-based feedback current setting. 49
2.13b Zeroed input, quantizer disconnected from loop and
dummy quantizer connected for proper loading. 49
2.13c One DAC enabled, all others disabled, quantizer clocked
to send impulse into loop. 49
2.13d Quantizer input voltage measured at sampling instants. 50
2.14a Typical output spectrum for SPICE prototype. 52
2.14b Typical output spectrum for C program using the same
parameters. 52
2.15 Examples of z-domain extraction from SPICE data. 55
2.16 First and second integrator output waveforms from SPICE
showing additional excess delay at sample 178. 56
2.17 Effect of quantizer metastability on excess loop delay. 57
3.1 Typical integrator output and quantizer waveforms. 62
3.2a Output spectrum using op amps with no slew-rate limiting. 63
3.2b Output spectrum using op amps with slew-rate limiting. 63
3.3 Ideal vs. real spectra in double integration modulators. 74
4.1 Example of high-speed double integration CT ∆ΣM. 75
4.2 Illustration of excess loop delay on NRZ DAC pulse. 76
4.3 Delayed NRZ pulse as a linear combination. 79
4.4 Linearized ∆ΣM with one-bit quantizer arbitrary gain κ. 81
4.5 Effect of loop delay on root locus of NTF( z, ). 82
d
4.6a Output spectrum from double integration CT ∆ΣM as
a function of excess delay. 83
4.6b In-band noise for zero input as a function of excess delay. 83
4.7 Maximum stable amplitude for double integration CT ∆ΣΜ. 84
4.8 Dynamic range for double integration CT ∆ΣΜ. 85
4.9a Dynamic range for multi-feedback BP CT ∆ΣΜ with
comparison to double integration results. 87
