Accurate Measurement of Power Consumption Overhead During FPGA Dynamic Partial Reconfiguration

1.5 MB·

by  Amor Nafkha

Accurate Measurement of Power Consumption
Overhead During FPGA Dynamic Partial
Reconfiguration
Amor Nafkha, and Yves Louet
CentraleSupe´lec/IETR, Campus de Rennes
Avenue de la Boulaie, CS 47601, 35576 Cesson Se´vigne´ Cedex, France.
Email: {amor.nafkha,yves.louet}@centralesupelec.fr
Abstract—In the context of embedded systems design, two speed of 400 MB/s that can be achieved by using Direct
important challengesarestillunderinvestigation. First,improve Memory Access (DMA) for data transfers between external
7 real-time data processing, reconfigurability, scalability, and self-
memory and the ICAP interface (clock speed of 100 MHz).
1 adjusting capabilities of hardware components. Second, reduce
In [9], authors use an over-clocking ICAP interface (clock
0 power consumption through low-power design techniques as
2 clock gating, logic gating, and dynamic partial reconfiguration speed of 133 MHz) and provide a maximum DPR measured
(DPR)capabilities.Today,severalapplication,e.g.,cryptography, speed of 418.5 MB/s.
n
a Software-definedradiooraerospacemissionsexploitthebenefits To the best of our knowledge, there is a few work which
J ofDPRofprogrammablelogicdevices.TheDPRallowswellde- address the experimental measurement and/or the power con-
finedreconfigurableFPGAregiontobemodifiedduringruntime.
0 sumption estimation duringthe DPR process. In [10], authors
However,itintroducesanoverheadintermofpowerconsumption
3
and time during the reconfiguration phase. In this paper, we presents a detailed investigation of power consumption of the

present an investigation of power consumption overhead of the DPRprocess.However,theyuseunderclockedICAPinterface
]
R DPRprocessusingahigh-speeddigitaloscilloscopeandtheshunt in order to catch power consumption during DPR given the
resistor method. Results in terms of reconfiguration time and
A factthatthepartialconfigurationtime isverysmall. Recently,
power consumption overhead for Virtex 5 FPGAs are shown.
. TexasInstrumentsprovidestheFusionDigitalPowerDesigner
s
software package [11] with the USB Interface Adapter EVM
c I. INTRODUCTION
[ [12]tomonitorreal-timepowerconsumptionvalues.However,
Software Defined Radio (SDR) refers to reconfigurable or this method did not provide high temporal resolution to mea-
1
re-programmable radios that can perform different function- suretheFPGApowerconsumptionduringDPRprocess.Inthe
v
9 ality with the same hardware [1], [2]. The main objective present paper, we will present a experimental approach using
4 is to produce communication devices which can support any high-speed digital oscilloscope and the shunt resistor method
8 wireless standards and services. The reconfigurability poses to provide power consumption during DPR process. One of
8 a set of new challenges in terms of real-time processing, the main results of this work is that the power consumption
0
power consumption, flexibility, performance. Consequently, overhead, during the FPGA dynamic partial reconfiguration,
.
1 many heterogeneous platforms composed of digital signal is low and doesn’t exceed 160 mW.
0
processors,applicationspecificintegratedcircuits,andFPGAs
The paper is structured as follows. Section II provides
7
have been developed to achieve sufficient processing power
1 introduction to different actors providing the utilization of
and flexibility. To cope with flexibility and computational
: Dynamic Partial reconfiguration concept. In order to make
v
issues, theconceptofFPGA DynamicPartialReconfiguration
i experimentalresultsmorerepresentative,variabledigitalfilters
X (DPR) can be used [3]–[8].
are introduced and implemented in Section III. Hardware
r The DPR is achieved by loading the partial bitstream of a architecture is providedin section IV. The experimentalsetup
a
new design into the SRAM-based FPGA configuration mem-
is introduced in Section V. The results of the experimentsare
ory and overwriting the current one. Thus the reconfigurable
presented and discussed in Section VI. Finally, Section VII
portionwillchangeitsbehavioraccordingtothenewlyloaded
provides a conclusion.
configuration. In this procedure, the reconfiguration time,
i.e. reconfiguration throughput, represents an important and
criticaldesignparameterwhichdeterminestheswitchingtime II. PARTIAL RECONFIGURATION
switching time between the two configuration. This factor
must be taken into accountin many cases where performance Xilinx company proposes two main FPGA family: Spartan
critical applications require fast switching of IP cores. To andVirtexdevices.Bothfamiliescansupportpartialreconfigu-
achieve runtime DPR, authors in [4] provide a high-speed rationthroughICAPcomponentinsidetheFPGA.Thesection
interface that transfers the DPR bitstreams into the Internal gives different actors providing the utilization of dynamic
Configuration Port (ICAP). They measured a maximum DPR partial reconfiguration design approach
A. The ICAP primitive after an initialization phase, due to the lost of the control of
reconfiguration process it self.
The ICAP allows to access to configurationdata and it has
the samesignalinginterfaceasSelectMAPandcanbeconfig- D. Enhancement ICAP architecture
uredin8or32bitsmode,dependingonthetargetdeviceuse.
Considering the inefficiency when the processor moves
The ICAP primitive is the hardwired FPGA logic by which
data to ICAP, we propose a design approach based on an
thebitstreamcanbedynamicallyloadedintotheconfiguration
appropriate architecture in charge of the partial bitstreams
memory. For partial reconfiguration management, we use an
management through the ICAP. We use the MicroBlaze to
embedded microprocessor (either MicroBlaze or PowerPC)
catchtheorderofreconfiguration.Partialbitstreamsarestored
to transmit the partial reconfiguration bitstream from storage
in a RAM and are accessible by the MicroBlaze through the
devices to ICAP in order to accomplish the reconfiguration
OPBEMC controller. Then bitstream dataflow is sent to the
process. The DPR feature allows to partially reconfigure the
ICAP component using one of the ICAP32 DMA IP. The
FPGA internalconfigurationlogic atthe runtime.As a conse-
ICAP32 DMA isan IPthatwe have developedin ourteam in
quence,aspecificdesignflowhastobeusedsoastodefinethe
order to take advantage of new 32 bit mode of Virtex 5. The
staticareas(whichwillnotchangeatruntime)andthedynamic
goalis to getcloser to the theoreticalthroughputof the ICAP
areas (which can be changed at runtime). This flow allows to
capacity,400MByte/s(ICAPrunningatamaximumfrequency
createpartialbitstreamsforthedynamicandstaticpart.These
of100MHz).TheMicroblazeisonlyusedforthesetupphase,
bitstreams are merged to give the global bitstream which is
after that, the IP works alone and acts like a DMA (Direct
mandatory for the initial global programming of the FPGA.
MemoryAccess) forbitstreamstransfersbetweenBRAM and
Then the dynamic part can be reconfigured using the partial
ICAP component.This IP is connected to the MicroBlaze via
bitstreams sent through the ICAP component at runtime.
the GPIO, and the ICAP component is configured in 32 bits
B. Partial reconfiguration manager mode.Specificregistersstorethestartaddressesandtheoffset
of the physicalmemory where partial bitstreams are stored in
To manage partial reconfiguration, we use an embedded
RAM. The MicroBlaze sends the order of reconfiguration to
processor soft core, called MicroBlaze, which is a reduced
the IP for the selected configuration, and the IP makes the
instruction set computer processor optimized for implementa-
memory transfer to the ICAP itself using a SRAM controller
tion on any Xilinx FPGA. Moreover,Xilinx providesthrough
includedinICAP32DMA component.So datawritingphases
Embedded Development Kit software an environment tool to
are realized by words of 32 bits at each FPGA clock cycle.
connectperipheralstotheMicroBlazeanddevelopapplication
program to drive it. Several communication ports (OPB bus, III. VARIABLE DIGITAL FILTERS
FSL links, PLB, LMB) are available. As mentioned before,
This section provides a detailed description of the imple-
partial reconfiguration is realized through ICAP component
mented design in order to make different measurements
inside the FPGA. This reconfiguration is possible by sending
partial bitstream to the ICAP. As a consequence,the different A. APT-VDF filter
bitstreams requiredhave to be stored in externalmemory like All-pass transformation based variable digital filter was
SRAM or internal FPGA memory like BRAM in the order initially proposed in [7]. Consider a prototype FIR filter with
to reduce writing and reading transfer during communication impulse response h(n) and its z-transform H(z). The APT-
mechanism to ICAP. In this paper, we use the Xilinx ML550 VDFversionofH(z)isobtainedbyreplacingeachunitdelay
board to make power and time overhead measurements of z with the first order all-pass structure, A(z), defined as
the dynamic partial reconfiguration process. We have made −1
−α+z
the choice to store the bitstreams in an internal dual-RAM A(z)= , |α|<1 (1)
1−αz−1
memory.
where α is the first order warping coefficient and its value
C. Partial reconfiguration modes determines the cut-off frequency of the APT-VDF filter. This
FPGA dynamic partial reconfiguration can be performed filtercanprovidevariablefrequencyresponsewithunabridged
externally, through the JTAG or SelectMap port, or internally controlovercut-offfrequency.TheadvantageoftheAPT-VDF
through ICAP component. These two modes takes the same filter is that it allows fine controlovercut-offfrequencywith-
configurationfilestoreconfigurethedesiredareainsideFPGA. out updating the filter coefficients or structure. The hardware
A restriction has to be made for the internal reconfiguration, architecture of the APT-VDF filter is depicted in figure 1.
where only partial reconfiguration can be made. Indeed, the In Fig. 1, the signals sel f1 and sel f2 are used to select
managementof the process of reconfigurationhas to be mon- which filter type will be created:
itored by a specific interface. For the external configuration, • Lowpass filter when sel f1 =0 and sel f2 =0,
this management could be realized by different components • Bandpass filter when sel f1 =1 and sel f2 =0,
like DSP or GPP. For the internal configuration, this could • Highpass filter when sel f1 =0 and sel f2 =1,
be managed by a hardware or a software processor as a • Bandstop filter when sel f1 =1 and sel f2 =1
MicroBlaze or a specific computing unit. As a consequence, Consider a Nth order lowpass prototype filter with cut-
for the internal case a global reconfiguration is impossible, off frequency fco, if 0 < α < 1, then the resultant cut-off
Fig.1. APT-basedVDFfilterarchitecture
frequenciesarelowerthanfco.Forα=0,thetransferfunction
oftheAPT-VDFfilterisequaltotheoriginaltransferfunction
of the prototype filter. If −1<α<0, then the resultant cut- Fig.2. Hardware architecture ofthedesigned system
offfrequenciesoftheAPT-CDFfilterarehigherthanfco.The
parameter α can be expressed as
logic that is necessary to each combination of sel f1 and
sin[(fco−fc)π/2]
α= (2) sel f2 parameters values. The VHDL code of the APT-VDF
sin[(fco+fc)π/2] filter is written in such a way that it is reusable. By changing
where fc is the cut-off frequency of the desired APT-VDF the filter’s order N, word length wl, and fractional length
filter. Given a desired frequencyresponse specifications, Mat- fl, an APT-VDF filter of any order and word length can be
lab filter design tool can be used to obtain the prototypefilter generated.TheModelSimtoolisusedtosimulateandvalidate
coefficients. the designed APT-VDF filter.
B. Floating to Fixed point conversion
IV. HARDWARE ARCHITECTURE
The APT-VDF architecture has been implemented in a
Virtex5 XC5VLX50T FPGA using fixed-pointrepresentation. The hardware architecture of the implemented APT-VDF
Herein, we consider the generalized fixed-point number rep- filter is shown in Fig. 2. This architecture was built on
resentation [wl,fl], where wl and fl correspond to the word Xilinx ML550 development board and designed using Xilinx
length and the fractional length of the number, respectively. ISE 14.7, XPS 14.7, and PlanAhead 14.7 environments. The
The difference il = wl − fl is referred to as the integer architecture contains the following components: Microblaze
lengthofthenumber.Inthispaper,theminimumintegerword processor, processor local bus (PLB), memory BRAM, local
length is calculated under large amounts of simulation data, memory bus (LMB), universal asynchronous receiver trans-
and the fractional word length are chosen through extensive mitter (UART RS232), multi-channel external memory con-
simulation and tolerable error limit. The root mean square troller (MCH EMC), and five general purpose input/output
error (RMSE) of output data between floating-point filter (GPIOs), true dual-port RAM, internal configuration access
and fixed-point filter is evaluated and it is considered as an portcontroller,the SR andRR regionsof the APT-VDFfilter.
optimizationcriteria.Duetothelimitationofspace,thisstudy The static region communicates with Microblaze via GPIO.
will not be presented in this paper. The input, output, and The UART is integrated to allow the communicationbetween
internal signals were representedas an integer and their word the Microblaze and the RS232 interface of the board. All the
length was varied in order to observe the effects of finite peripherals communicate with the Microblaze via the PLB
precision.SimulationsusingaserialconfigurationoftheAPT- bus. The memory space of the BRAM is configured to be
VDF filter at different precisions were made. The results are 16 KBytes. The on-chip dual-port RAM is configured to 128
shown that 12-bit word length and 10-bit fractional precision Kbytes and it is used to store the partial bitstream files. The
has significant root mean square error (RMSE ≈ −32dB), host PC is responsible for transferring those bitstream files
whereas 16-bit word length and 14-bit fractional precision or to the Microblaze through the UART. The ICAP32 DMA IP
higherprecisionresultsinverylowerror(RMSE ≈−44dB). is used to take advantage of the 32-bit mode of virtex5. The
goalis to getcloser to the theoreticalthroughputof the ICAP
C. VHDL Implementation
capacity,400MByte/s(ICAPrunningatamaximumfrequency
The APT-VDF filter has to be implemented in such a way of 100MHz). The Microblaze is only used for the setup
that the design has a static region (SR) and a reconfigurable phase, after that, the ICAP32 DMA IP controller operates
region(RR) whichdependson parameterssel f1 andsel f2. autonomously,and it acts as direct memory access for partial
In this work, we assume that the parameter α is known and bitstream files transfer between the dual-port RAM and the
fixed. The static region of the APT-VDF filter contains the ICAP component. The ICAP32 DMA IP is connected to the
prototype filter structure and the all-pass filter given the fact MicroBlaze through a general purpose input/output interface.
that the parameter α is known. Both filters coefficients are Two specific registersare usedto storethe startaddressesand
given as constants in the hardware architecture.The reconfig- theoffsetofthephysicalmemorywherepartialbitstreamfiles
urable region of the APT-VDF filter contains the minimum are stored.
Fig.3. AD620amplification circuit.
V. EXPERIMENTALSETUP
TheML550evaluationboardshavebeenused inthisstudy.
Itiswellsuitedtopowerconsumptionmeasurementforseveral
reasons. Thisboardprovidesus with 5 powerrails (core,IOs,
peripherals) and current sense resistors which would simplify
the experimental measurement. The recommended Virtex5
Fig.4. Placement oftop-level modules.
corevoltage,designatedVCCINT,is1.0±10%V.Depending
on the input/output standard being implemented, the Virtex5
TABLEI
I/O voltage supply, designated VCCO, can vary from 1.2 FPGAPHYSICALRESOURCESOFTHERECONFIGURABLEREGION
V to 3.3 V. Moreover, Xilinx defines an auxiliary voltage,
VCCAUX, which is recommendedto operate at 2.5 ± 10%V Resources Highpass Bandpass
tosupplyFPGAclockresources.Theboardhostsatwoheader LUT/FD 315/0 336/336
connector which provides test points for the ML550 power SliceL/SliceM 67/23 77/26
regulators.Moreover,tomeasuredifferentcurrentsdrainedby Frames 16 16
the FPGA, the ML550 board contains a series of shunt 10 FrameRegion 2 2
mΩ ± 1% 3W Kelvin currentsense resistors on each voltage Bitstream 94464Bytes 94464Bytes
regulator lines. Thus, the current will be the voltage across
the shunt resistor divided by the resistance value itself. Since
thesensitivityoftheVCCINT,VCCO, andVCCAUX sensors
frequency. Consider a prototype lowpass filter where the cut-
are pretty low (0.5-2mV), voltage amplifiers are needed. To
off frequency,the transition bandwidth, the passband, and the
this end, we have used integrated instrumentation amplifiers
stopband ripple specifications are 0.08, 0.14, 0.8 dB, and -
AD620, from Analog Devices. The AD620 has a feature to
40 dB, respectively. Using the filter design and analysis tool
increasegainbetween1-10.000timeswithanexternalresistor.
anddirect-formFIRstructure,theorderofgeneratedprototype
Thoseamplifiersallowtoregulatethegainonlybychanginga
filter is equal to N =21.
single resistance, called RG. We wanted to reach a voltage of
about100-400mV,attheoutputofthevoltageamplifierthen,
according to the component’s availability of the laboratory,
A. DPR area
was established gains of about 100 and 1000 to amplify the
VCCINT and the VCCO voltages using resistances of 483
The partial reconfiguration module has been implemented
Ω, and 49 Ω. Fig. 3 shows the developed circuit board to using the Xilinx PlanAhead tool. The Design view shows the
amplify VCCINT and VCCO voltages. The input voltages
placementof each instance and the post-place information,as
are connected to a 2 x 13 0.1-inch male header connector
shown in fig. 4.
which provides test points for the ML550 power regulators.
Table I summarizes the key (post-place-and-route) imple-
TheTektronixTDS2024Coscilloscopeisbeingusedtodisplay
mentationresultsofthereconfigurableregionwhenthecouple
the voltages output from the two AD620 amplifiers.
ofparameters(sel f1,sel f2)isequalto(0,1)and(1,1),re-
spectively.Theresultsarecoherentwithourexpectationgiven
VI. EXPERIMENTALRESULTS
the fact that when sel f1 =0 and sel f2 = 1, the generated
In this section, the implementation results and power con- APT-VDFfilterisequivalenttohighpassfilter.However,when
sumptionmeasurementsof the APT-VDF filter are givenwith sel f1 = 1 and sel f2 = 1, the generated APT-VDF filter is
the help of a suitable design example. Herein, all mentioned equivalent to a bandstop filter, which requires to insert Nwl
frequenciesarenormalizedwithrespecttohalfofthesampling delay units.
TABLEIII
B. DPR timing overhead
TOTALFPGAPHYSICALRESOURCESUSAGEANDPOWERCONSUMPTION
ESTIMATIONUNDERTWOCONFIGURATIONS
The FPGA devices are composed of columns and rows.
The biggest advantage brought by the recent Virtex family Resources
is that the reconfigurationcan be realized by frames, contrary (sel f1,sel f2) (0,1) (1,1)
to Virtex II whichimposed to reconfigurethe wholecolumns. Slices 2364/7200 2427/7200
This improvementgives more flexibility on the modularity of
Registers 3843/28800 4179/28800
the design flow during the placement phase of the dynamic
LUTS 4850/28800 4998/28800
and static parton the floorplanof the device.Frame by frame
St.power 450mW 450mW
reconfiguration can significantly reduce the size of the gener-
Dy.power 256mW 270mW
ated partial reconfiguration files, and hence the configuration
Totalpower 707mW 720mW
time overhead.
Table II presents the experimental FPGA reconfiguration
timeneededtoperformAPT-VDFfilterreconfiguration.Three
reconfiguration approaches are used:
• Full FPGA reconfiguration: we use JTAG connector to
configure the FPGA with a total pre-made bitstream.
• External partial FPGA reconfiguration: we use JTAG
connector to configure just the reconfigurable region of
the APT-VDF filter with a pre-made partial bitstream
• Internal partial FPGA reconfiguration: we use the
ICAP32 DMA IP to configure just the reconfigurable
region of the APT-VDF filter with a pre-made partial
bitstream.
TABLEII
EXPERIMENTALRESULTSONRECONFIGURATIONTIMEOVERHEAD
Reconf. type Bitstream Reconf. time
Full(JTAG) 1716KB 3.80s
Fig.5. FPGAcorepowerconsumptionduringtotalreconfiguration
Partial (JTAG) 94.464KB 208.9ms
Partial(ICAP32DMA) 94.464KB 324µs
MicroBlaze is only used to configure specific registers
whichgivethebeginningaddressandtheoffsetinRAMwhere
partialbitstreamsarestored.Asaconsequence,weachievethe
maximum theoretical input throughput of the ICAP32 DMA
which equal to 400 MB/s. We send a word each clock cycle,
but due to registers loading and experimental uncertainty, we
have an constant overhead of around 80 µs.
C. DPR power consumption overhead
The overall resource required to implement the designed
system is given in table III. Moreover,the static and dynamic
power consumption of the design mapped on FPGA can be
estimated using the Xilinx XPower analyser tool.
Fig.5andFig.6showthepowerconsumptionoftheFPGA
Fig.6. FPGAcorepowerconsumption duringpartial reconfiguration
core during total reconfiguration and partial reconfiguration
processes, respectively. The power consumption overhead is
givenbyVCCINTvoltagevalue.Duringtotalreconfiguration,
VII. CONCLUSIONS
the power consumption of the FPGA core is stable around
220mW, otherwiseitis around360mW. Duringthedynamic Based on experiment measurement, this paper presents the
partialreconfigurationphaseoftheAPT-VDFfilter,theFPGA FPGA core power consumption overhead during the dynamic
power consumption overhead overhead doesn’t exceed 160 partial reconfiguration.Three main conclusions can be drawn
mW (500 mW - 340 mW) during 324 µs. from our analysis. First, the FPGA dynamic partial recon-
figuration is an efficient design technique which permits to
changea partofthe deviceswhile the restofan FPGA is still
running. Moreover, this technique can reduce dynamic and
static power consumptionin comparisonwith the well-known
parametrization design approach. Second, the reconfiguration
time is very small (around 324 µs for a partial bitstream
size equal to 95Kbytes). Third, as we know, the DPR will
introducepowerconsumptionoverhead.Thisworkshowsthat
this overhead is small.
VIII. ACKNOWLEDGMENT
The present work was carried out within the framework of
Celtic-Plus SHARING project (number C2012/1-8).
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