16-Bit 40/80 MSPS ADCs with LVDS/CMOS Outputs

54 Pages·2016·1.5 MB·English

ADS5560
ADS5562
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16-BIT, 40/80 MSPS ADCs WITH DDR LVDS/CMOS OUTPUTS
FEATURES • Internal/ExternalReferenceSupport
1
• 16-BitResolution • 3.3-VAnalog andDigitalSupply
• MaximumSampleRate • Pin-for-pinwithADS5547Family
– ADS5562-80MSPS • 48-QFNPackage(7mm· 7mm)
– ADS5560-40MSPS
APPLICATIONS
• TotalPower
• Medical Imaging- MRI
– 865mWat80MSPS
• WirelessCommunicationsInfrastructure
– 674mWat40MSPS
• SoftwareDefinedRadio
• NoMissingCodes
• TestandMeasurement Instrumentation
• HighSNR84dBFS (3MHzIF) • HighDefinitionVideo
• 85dBcSFDR(3MHzIF)
• LowFrequencyNoiseSuppressionMode
• ProgrammableFineGain,1dBstepstill6dB
• DoubleDataRate(DDR)LVDSandParallel
CMOSOutputOptions
DESCRIPTION
ADS556X is a high performance 16-bit A/D converter family with sampling rates up to 80 MSPS. It supports very
high SNR for input frequencies in the first Nyquist zone. The device includes a low frequency noise suppression
modethatimprovesthenoisefromdctoabout 1MHz.
Inadditiontohigh performance, the device offers several flexible features such as output interface (either Double
DataRateLVDS orparallelCMOS)andfinegain(in1dBstepstill6dB).
Innovative techniques, such as DDR LVDS and an internal reference that does not require external decoupling
capacitors, have been used to achieve significant savings in pin-count. This results in a compact 7 mm x 7 mm
48pinQFNpackage.
The device can be put in an external reference mode, where the VCM pin behaves as the external reference
input. For applications where power is important, ADS556X offers power down modes and automatic power
scalingatlowersample rates.
Itisspecifiedovertheindustrialtemperaturerange(-40(cid:176) Cto +85(cid:176) C).
1
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof
TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2008,TexasInstrumentsIncorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarilyincludetestingofallparameters.
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ADS5562
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D D
D D D N
D N V G
V G R R
A A D D
CLKP CLKOUTP
CLOCKGEN
CLKM CLKOUTM
D0_D1_P
D0_D1_M
D2_D3_P
D2_D3_M
D4_D5_P
INP Sample Digital D4_D5_M
Encoder
and 16-BitADC
and
Hold D6_D7_P
INM Serializer
D6_D7_M
D8_D9_P
D8_D9_M
D10_D11_P
VCM Reference Control D10_D11_M
Interface
D12_D13_P
D12_D13_M
D14_D15_P
D14_D15_M
OVR
ADS556x
K N A T E S E
L E T E O F D
C S A S D O
S SD RE M
LVDS INTERFACE
B0095-05
PACKAGE/ORDERINGINFORMATION(1)
PRODUCT PACKAGE- PACKAGE SPECIFIED PACKAGE ORDERING TRANSPORT
LEAD DESIGNATOR TEMPERATURE MARKING NUMBER MEDIA
RANGE
ADS5562 QFN-48 RGZ –40(cid:176) Cto85(cid:176) C AZ5562 ADS5562IRGZT TapeandReel,
small
ADS5562IRGZR TapeandReel,
large
ADS5560 QFN-48 RGZ –40(cid:176) Cto85(cid:176) C AZ5560 ADS5560IRGZT TapeandReel,
small
ADS5560IRGZR TapeandReel,
large
(1) q =25.41(cid:176) C/W(0LFMAirFlow),q =16.5(cid:176) C/Wwhenusedwith2oz.coppertraceandthethermalpadissoldereddirectlytoa
JA JC
JEDECstandardfourlayer3in.x3in.(7.62cmx7.62cm)PCB.Thermalpadis5.2x5.2mm.Pleaseseemechanicaldrawingsinthe
backofthedatasheetfordetails.
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ABSOLUTE MAXIMUM RATINGS(1)
overoperatingfree-airtemperaturerange(unlessotherwisenoted)
VALUE UNIT
AVDD Supplyvoltagerange –0.3Vto3.9 V
DRVDD Supplyvoltagerange –0.3Vto3.9 V
VoltagebetweenAGNDandDRGND -0.3to0.3 V
VoltagebetweenAVDDtoDRVDD -0.3to3.3 V
VoltageappliedtoVCMpin(inexternalreferencemode) -0.3to1.8 V
Voltageappliedtoanaloginputpins –0.3Vtominimum(3.6,AVDD+0.3V) V
T Operatingfree-airtemperaturerange –40to85 (cid:176) C
A
T Operatingjunctiontemperaturerange 125 (cid:176) C
jmax
T Storagetemperaturerange –65to150 (cid:176) C
STG
Leadtemperature1,6mm(1/16")fromthecasefor10seconds 220 (cid:176) C
(1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings
onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating
conditionsisnotimplied.Exposuretoabsolutemaximumratedconditionsforextendedperiodsmayaffectdevicereliability.
RECOMMENDED OPERATING CONDITIONS
overoperatingfree-airtemperaturerange(unlessotherwisenoted)
MIN TYP MAX UNIT
SUPPLIESANDREFERENCES
AVDD Analogsupplyvoltage 3 3.3 3.6 V
DRVDD Digitalsupplyvoltage 3 3.3 3.6 V
ANALOGINPUTS
Differentialinputvoltagerange(withdefaultfinegain=1dB) 3.56 V
PP
Inputcommon-modevoltage 1.5±0.1 V
VoltageappliedonVCMinexternalreferencemode 1.5 V
±0.05
CLOCKINPUT
Samplerate DEFAULTSPEEDmode >30 80 MSP
S
ADS5562
LOWSPEEDmode (1) 1 30 MSP
S
DEFAULTSPEEDmode >30 40 MSP
S
ADS5560
LOWSPEEDmode 1 30 MSP
S
Sinewave,LVPECL,
Supportedclockwaveformformats
LVDS,LVCMOS
Clockamplitude,ac-coupled,differential(V -V ) 0.4 V
CLKP CLKM PP
Clockdutycycle 45% 50% 55%
DIGITALOUTPUTS
C MaximumexternalloadcapacitancefromeachoutputpintoDRGND(LVDSandCMOS 5 pF
L
modes)
R DifferentialexternalloadresistancebetweentheLVDSoutputpairs(LVDSmode) 100 Ω
L
Operatingfree-airtemperature -40 85 (cid:176) C
(1) SeeLowsamplingfrequencyoperationinapplicationsectionfordetails.
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ELECTRICAL CHARACTERISTICS
Typicalvaluesareat25(cid:176) C,AVDD=DRVDD=3.3V,samplingrate=MaxRated,sinewaveinputclock,1.5V clock
PP
amplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,internalreferencemode,DDRLVDSinterface,defaultfine
gain(1dB).
MinandmaxvaluesareacrossthefulltemperaturerangeT =–40(cid:176) CtoT =85(cid:176) C,AVDD=DRVDD=3.3V,sampling
MIN MAX
rate=MaxRated,unlessotherwisenoted.
TEST ADS5562 ADS5560
PARAMETER UNIT
CONDITIONS MIN TYP MAX MIN TYP MAX
RESOLUTION 16 16 bits
ANALOGINPUT
Differentialinputvoltage V
range (1) 3.56 3.56 PP
Differentialinput 5 5 pF
capacitance
Analoginputbandwidth 300 300 MHz
Analoginputcommon 6.6 6.6 m A/MSPS
modecurrent(perinputpin)
VCM Commonmodeoutput Internalreference 1.5 1.5 V
voltage mode
VCMoutputcurrent Internalreference ±4 ±4 mA
capability mode
DCACCURACY
NoMissingCodes 0dBgain Assured Assured
DNL Differentialnon-linearity -0.95 0.5 3 -0.95 0.5 3 LSB
INL Integralnon-linearity -8.5 ±3 8.5 -8.5 ±3 8.5 LSB
Offseterror -25 ±10 25 -25 ±10 25 mV
Offseterrortemperature 0.005 0.005 mV/(cid:176) C
coefficient
Variationofoffseterror 1.5 1.5 mV/V
acrossAVDDsupply
Therearetwosourcesofgainerror:i)internalreferenceinaccuracyandii)channelgain
error
E Gainerrorduetointernal -2.5 ±1 2.5 -2.5 ±1 2.5 %FS
GREF
referenceinaccuracyalone
E Channelgainerroralone -2.5 ±1 2.5 -2.5 ±1 2.5 %FS
CHAN
Channelgainerror 0.01 0.01 Δ%/(cid:176) C
temperaturecoefficient
POWERSUPPLY
IAVDD Analogsupplycurrent 210 250 160 190 mA
LVDSmode 52 44 mA
I =3.5mA,R =
O L
IDRVDD Digitalsupplycurrent 100Ω
C =5pF
L
CMOSmode 60 37 mA
F =3MHz
IN
Totalpower LVDSmode 865 1100 674 810 mW
Standbypower STANDBYmode 155 135 mW
withclockrunning
Clockstoppower 125 150 125 150 mW
(1) Thefull-scalevoltagerangeisafunctionofthefinegainsettings.SeeTable23.
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ELECTRICAL CHARACTERISTICS (Continued)
Typicalvaluesareat25(cid:176) C,AVDD=DRVDD=3.3V,samplingrate=MaxRated,sinewaveinputclock,1.5V clock
PP
amplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,internalreferencemode,DDRLVDSinterface,0dBfine
gain (1).
MinandmaxvaluesareacrossthefulltemperaturerangeT =–40(cid:176) CtoT =85(cid:176) C,AVDD=DRVDD=3.3V,sampling
MIN MAX
rate=MaxRated,defaultfinegain(1dB),unlessotherwisenoted.
ADS5562 ADS5560
PARAMETER TESTCONDITIONS Fs=80MSPS Fs=40MSPS UNIT
MIN TYP MAX MIN TYP MAX
ACCHARACTERISTICS
F =3MHz 84 84.3
IN
FIN=10MHz LVDS 79 83.8 80 84
dBFS
F =25MHz interface 83.2 82.5
IN
SNR F =30MHz 82.8 81.8
IN
Signaltonoise
ratio FIN=3MHz 81.7 83.5
FIN=10MHz CMOS 77 81.4 78 83.1
dBFS
F =25MHz interface 80.7 81.8
IN
F =30MHz 80.4 81.6
IN
RMSoutputnoise Inputstiedtocommon-mode 1.42 1.42 LSB
F =3MHz 80.5 83.2
IN
FIN=10MHz LVDS 75 80.5 76 83
dBFS
F =25MHz interface 79.5 79
IN
SINAD F =30MHz 79 77
IN
Signaltonoiseand
distortionratio FIN=3MHz 80.5 82
FIN=10MHz CMOS 73.5 80.2 75 81.4
dBFS
F =25MHz interface 79.3 79.3
IN
F =30MHz 77.9 78
IN
ENOB
LVDS
Effectivenumber F =10MHz 12.2 13.1 12.4 13.5 bits
IN interface
ofbits
F =3MHz 85 90
IN
SFDR F =10MHz 77 85 78 88
IN
Spuriousfree dBc
dynamicrange FIN=25MHz 83 83
F =30MHz 80 79
IN
F =3MHz 90 94
IN
HD2 FIN=10MHz 77 89 78 92
dBc
Secondharmonic F =25MHz 88 90
IN
F =30MHz 88 88
IN
(1) Notethatafterreset,thedeviceisinitializedto1dBfinegainsetting.ForSFDRandSNRperformanceacrossfinegains,seeTypical
Characteristicssection.
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ELECTRICAL CHARACTERISTICS (Continued)
Typicalvaluesareat25(cid:176) C,AVDD=DRVDD=3.3V,samplingrate=MaxRated,sinewaveinputclock,1.5V clock
PP
amplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,defaultfinegain(1dB),internalreferencemode,DDR
LVDSinterface0dBfinegain(1).
MinandmaxvaluesareacrossthefulltemperaturerangeT =–40(cid:176) CtoT =85(cid:176) C,AVDD=DRVDD=3.3V,sampling
MIN MAX
rate=MaxRated,defaultfinegain(1dB),unlessotherwisenoted.
ADS5562 ADS5560
PARAMETER TESTCONDITIONS UNIT
MIN TYP MAX MIN TYP MAX
F =3MHz 85 90
IN
HD3 FIN=10MHz 77 85 78 88
dBc
Thirdharmonic F =25MHz 83 83
IN
F =30MHz 80 79
IN
F =3MHz 104 104
IN
Worstharmonic F =10MHz 102 102
IN
otherthanHD2, dBc
HD3 FIN=25MHz 100 101
F =30MHz 100 101
IN
F =3MHz 84 88
IN
THD F =10MHz 75.5 83 76.5 86
IN
Totalharmonic dBc
distortion FIN=25MHz 82 81
F =30MHz 80 78
IN
IMD
Two-tone F =5MHz,F =10MHz
IN1 IN2 92 98 dBFS
intermodulation eachtone-7dBFS
distortion
Voltageoverload Recoveryto1%for6-dB 1 1 clock
recoverytime overload cycles
(1) Notethatafterreset,thedeviceisinitializedto1dBfinegainsetting.ForSFDRandSNRperformanceacrossfinegains,seeTypical
Characteristicssection.
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DIGITAL CHARACTERISTICS
DCspecificationsrefertotheconditionwherethedigitaloutputsarenotswitching,butarepermanentlyatavalidlogiclevel0
or1,AVDD=3.0Vto3.6V,I =3.5mA,R =100Ω(1)(2)
O L
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
DIGITALINPUTS
High-levelinputvoltage 2.4 V
Low-levelinputvoltage 0.8 V
High-levelinputcurrent 33 m A
Low-levelinputcurrent -33 m A
Inputcapacitance 4 pF
DIGITALOUTPUTS–CMOSMODE
High-leveloutputvoltage DRVDD V
Low-leveloutputvoltage 0 V
Outputcapacitance Capacitanceinsidethedevicefromeachoutputpinto 4 pF
ground
DIGITALOUTPUTS–LVDSMODE
V High-leveloutputvoltage +350 mV
ODH
V Low-leveloutputvoltage -350 mV
ODL
V Outputcommon-mode 1.2 V
OCM
voltage
Outputcapacitance Capacitanceinsidethedevicefromeachoutputpinto 4 pF
ground
(1) AllLVDSandCMOSspecificationsarecharacterized,butnottestedatproduction.
(2) I referstotheLVDSbuffercurrentsetting;R isthedifferentialloadresistancebetweentheLVDSoutputpair.
O L
DnD_nD_nD +n +11__PP
Logic 0 Logic 1
V =–350 mV* V = 350 mV*
ODL ODH
DnD_Dn_nD +n 1+_1M_M
V
OCM
V
GGNNDD
*Withexternal100-Wtermination
T0334-01
Figure1. LVDSOutput VoltageLevels
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TIMING CHARACTERISTICS – LVDS AND CMOS MODES(1)
Typicalvaluesareat25(cid:176) C,AVDD=3.3V,DRVDD=3.0to3.6V,Samplingfrequency=80MSPS,sinewaveinputclock,
50%clockdutycycle,1.5V clockamplitude,C =5pF(2),nointernaltermination,I =3.5mA,R =100Ω (3)
PP L O L
MinandmaxvaluesareacrossthefulltemperaturerangeT =–40(cid:176) CtoT =85(cid:176) C,AVDD=DRVDD=3.0to3.6V,
MIN MAX
unlessotherwisenoted.
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
t Aperturedelay 0.5 1.2 2 ns
a
Samplingfrequency=80MSPS 90 fsrms
t Aperturejitter
j
Samplingfrequency=40MSPS 135 fsrms
Timetodatastable (4)aftercomingoutofSTANDBYmode 60 200 m s
Wake-uptime
Timetovaliddataafterstoppingandrestartingtheinputclock 80 m s
Clock
Latency 16
cycles
DDRLVDSMODE(5)
LVDSbitclockduty 47% 50% 53%
cycle
t Datasetuptime(6) Datavalid(7)tozero-crossingofCLKOUTP 2.0 3.0 ns
su
t Dataholdtime(6) Zero-crossingofCLKOUTPtodatabecominginvalid(7) 2.0 3.0 ns
h
t Clockpropagationdelay Inputclockrisingedgecross-overtooutputclockrisingedge 9.5 11 12.5 ns
PDI
cross-over
t Datarisetime Risetimemeasuredfrom–100mVto100mV 0.15 0.22 0.3 ns
r
t Datafalltime Falltimemeasuredfrom100mVto–100mV 0.15 0.22 0.3 ns
f
t Outputclockrisetime Risetimemeasuredfrom–100mVto100mV 0.15 0.22 0.3 ns
r
t Outputclockfalltime Falltimemeasuredfrom100mVto–100mV 0.15 0.22 0.3 ns
f
t Outputenable(OE)to TimetodatavalidafterOEbecomesactive 700 ns
OE
datadelay
PARALLELCMOSMODE
CMOSoutputclockduty 50%
cycle
t Datasetuptime Datavalid(8)to50%ofCLKOUTrisingedge 6.5 8.0 ns
su
th Dataholdtime 50%ofCLKOUTrisingedgetodatabecominginvalid(8) 2.0 3.0 ns
t Clockpropagationdelay Inputclockrisingedgecross-overto50%ofCLKOUTrising 6.3 7.8 9.3 ns
PDI
edge
t Datarisetime Risetimemeasuredfrom20%to80%ofDRVDD 1.0 1.5 2.0 ns
r
t Datafalltime Falltimemeasuredfrom80%to20%ofDRVDD 1.0 1.5 2.0 ns
f
t Outputclockrisetime Risetimemeasuredfrom20%to80%ofDRVDD 0.7 1.0 1.2 ns
r
t Outputclockfalltime Falltimemeasuredfrom80%to20%ofDRVDD 1.2 1.5 1.8 ns
f
t Outputenable(OE)to TimetodatavalidafterOEbecomesactive 200 ns
OE
datadelay
(1) Timingparametersareensuredbydesignandcharacterizationandnottestedinproduction.
(2) C istheeffectiveexternalsingle-endedloadcapacitancebetweeneachoutputpinandground.
L
(3) IoreferstotheLVDSbuffercurrentsetting;R isthedifferentialloadresistancebetweentheLVDSoutputpair.
L
(4) DatastableisdefinedasthepointatwhichtheSNRiswithin2dBofitsnormalvalue.
(5) Measurementsaredonewithatransmissionlineof100Ωcharacteristicimpedancebetweenthedeviceandtheload.
(6) Setupandholdtimespecificationstakeintoaccounttheeffectofjitterontheoutputdataandclock.
(7) Datavalidreferstologichighof+100mVandlogiclowof-100mV.
(8) Datavalidreferstologichighof2.6Vandlogiclowof0.66V.
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Table1.TimingCharacteristicsatlowersamplingfrequencies
Sampling
Frequency, t ,Setuptime,ns t ,Holdtime,ns t ,Clockpropagationdelay,ns
su ho PDI
MSPS
DDRLVDS
65 2.7 3.7 2.7 3.7 11.5 13 14.5
40 5 6 5 6 16.5 18 19.5
20 8 11 8 11 30.5 32 33.5
ParallelCMOS
65 8 9.5 3 4 7 8.5 10
40 14 15.5 6.5 7.5 8 9.5 11
20 14 6.5 5 10.5 15
N+3 N+4 N+18 N+19
N+2 N+17
Sample N+1 N+16
N
Input
Signal
t
a
CLKP
Input
Clock
CLKM
CLKOUTM
CLKOUTP
t
su
t
16 Clock Cycles th PDI
DDR
LVDS
Output Data
E O E O E O E O E O E O E O E O E O E O
DXP, DXM
N–16 N–15 N–14 N–13 N–12 N–1 N N+1 N+2
E–EvenBitsD0,D2,D4,D6,D8,D10,D12,D14
O–OddBitsD1,D3,D5,D7,D9,D11,D13,D15
t
PDI
CLKOUT
t
su
Parallel
CMOS 16 Clock Cycles th
Output Data
N–16 N–15 N–14 N–13 N–12 N–1 N N+1 N+2
D0–D15
T0105-08
Figure2.Latency
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CLKM
Input
Clock
CLKP
t
PDI
CLKOUTP
Output
Clock
CLKOUTM
t t
h su
t t
su h
Output Dn_Dn+1_P, (1) (2)
Dn Dn+1
Data Pair Dn_Dn+1_M
(1)
Dn –Bits D0, D2, D4, D6, D8, D10, D12, D14
(2)
Dn+1–Bits D1, D3, D5, D7, D9, D11, D13, D15
T0106-06
Figure3. LVDSModeTiming
CLKM
Input
Clock
CLKP
t
PDI
Output
CLKOUT
Clock
t
h
t
su
Output (1)
Dn Dn
Data
(1)
Dn–Bits D0–D15
T0107-04
Figure4.CMOSModeTiming
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