16-Bit, 250kSPS, Serial, CMOS, Sampling ADC - Texas Instruments

31 Pages·2014·0.64 MB·English

ADS8519
www.ti.com SLAS462D–JUNE2007–REVISEDSEPTEMBER2010
16-Bit, 250kSPS, Serial, CMOS, Sampling
ANALOG-TO-DIGITAL CONVERTER
CheckforSamples:ADS8519
FEATURES DESCRIPTION
1
• 0Vto8.192V,±5V,and ±10VInputRanges The ADS8519 is a complete 16-bit sampling
23
• 93dBSNRwith20kHzInput analog-to-digital (A/D) converter using state-of-the-art
CMOS structures. It contains a complete 16-bit,
• ±1.5LSBMaxINL
capacitor-based, successive approximation register
• ±1LSBMaxDNL;16Bits, NoMissingCodes
(SAR) A/D converter with sample-and-hold,
• SPI™-CompatibleSerialOutputwith reference, clock, and a serial data interface. Data can
Daisy-Chain(TAG)Featureand 3-StateBus be output using the internal clock or synchronized to
an external data clock. The ADS8519 also provides
• 5VAnalogSupply,1.65Vto5.25VI/OSupply
an output synchronization pulse for ease-of-use with
• PinoutSimilar to16-BitADS7809(Low-Speed)
standardDSPprocessors.
and12-BitADS7808and ADS8508
The ADS8519 is specified at a 250kSPS sampling
• NoExternalPrecisionResistorsRequired
rateoverthefulltemperaturerange. Internalprecision
• UsesInternalor ExternalReference resistors provide various input ranges including ±10V,
• 110mWTypPowerDissipationat250kSPS ±5V, and 0V to 8.192V, while the innovative design
allows operation from a single 5V supply with power
• 28-PinSSOPPackage
dissipationunder125mW.
• SimpleDSPInterface
The ADS8519 is available in a 28-pin SSOP
package, and is fully specified for operation over the
APPLICATIONS
industrial–40°Cto+85°Ctemperaturerange.
• IndustrialProcessControl
• DataAcquisitionSystems
• DigitalSignalProcessing
• MedicalEquipment
• Instrumentation
Successive Approximation Register
Clock EXT/INT
7kW CDAC
R1IN
7kW BUSY
R2IN Serial DATACLK
2.87kW
R3IN 25.67kW Comparator DOautta TAG
and DATA
CAP Control R/C
Buffer Internal SB/BTC
+4.096V Ref CS
4kW
PWRD
REF
1
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas
Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
SPIisatrademarkofMotorola,Inc.
2
Allothertrademarksarethepropertyoftheirrespectiveowners.
3
PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2007–2010,TexasInstrumentsIncorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarilyincludetestingofallparameters.
ADS8519
SLAS462D–JUNE2007–REVISEDSEPTEMBER2010 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage.
ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore
susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications.
PACKAGE/ORDERINGINFORMATION(1)
MINIMUM NO MINIMUM SPECIFIED
INL MISSING SINAD TEMPERATURE PACKAGE- PACKAGE ORDERING TRANSPORT
PRODUCT (LSB) CODES (dB) RANGE LEAD DESIGNATOR NUMBER MEDIA,QTY
ADS8519IBDB Tube,50
ADS8519IB ±1.5 16-Bit 90 –40°Cto+85°C SSOP-28 DB
ADS8519IBDBR TapeandReel,2000
ADS8519IDB Tube,50
ADS8519I ±3 15-Bit 87 –40°Cto+85°C SSOP-28 DB
ADS8519IDBR TapeandReel,2000
(1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI
websiteatwww.ti.com.
ABSOLUTE MAXIMUM RATINGS(1) (2)
Overoperatingfree-airtemperaturerange(unlessotherwisenoted).
UNIT
R1 ±25V
IN
R2 ±25V
IN
Analoginputs
R3 ±25V
IN
REF +V +0.3VtoAGND2–0.3V
ANA
DGND,AGND2 ±0.3V
Groundvoltagedifferences V 6V
ANA
V 6V
DIG
Digitalinputs –0.3Vto+V +0.3V
DIG
Internalpowerdissipation 700mW
Maximumjunctiontemperature +165°C
Leadtemperature(soldering,10s) +300°C
(1) StressesabovethoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Exposuretoabsolute
maximumconditionsforextendedperiodsmayaffectdevicereliability.
(2) Allvoltagevaluesarewithrespecttonetworkgroundterminal.
ELECTRICAL CHARACTERISTICS
AtT =–40°Cto+85°C,f =250kSPS,andV =V =5V,usinginternalreference(unlessotherwisespecified).
A s DIG ANA
ADS8519I ADS8519IB
PARAMETER TESTCONDITIONS MIN TYP MAX MIN TYP MAX UNIT
Resolution 16 16 Bits
ANALOGINPUT
Voltageranges(1)
Impedance(1)
Capacitance 50 50 pF
THROUGHPUTSPEED
Conversioncycletime Acquireandconvert 4 4 ms
Throughputrate 250 250 kSPS
(1) ±10V,±5V,0Vto8.192V,etc.(seeTable2)
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ELECTRICAL CHARACTERISTICS (continued)
AtT =–40°Cto+85°C,f =250kSPS,andV =V =5V,usinginternalreference(unlessotherwisespecified).
A s DIG ANA
ADS8519I ADS8519IB
PARAMETER TESTCONDITIONS MIN TYP MAX MIN TYP MAX UNIT
DCACCURACY
INL Integrallinearityerror –3 3 –1.5 1.5 LSB(2)
DNL Differentiallinearityerror –2 2 –1 1 LSB
Nomissingcodes 15 16 Bits
Transitionnoise(3) 0.67 0.67 LSB
Full-scale ±10Vrange Internalreference –0.5 0.5 –0.25 0.25
error(4)(5) Allotherranges Internalreference –0.5 –0.05 0.5 –0.5 –0.05 0.5 %FSR
Full-scaleerrordrift Internalreference ±7 ±7 ppm/°C
Full-scale ±10Vrange Externalreference –0.05 0.003 0.05 –0.05 0.003 0.05
error(4)(5) Allotherranges Externalreference –0.5 0.5 –0.5 0.5 %FSR
Full-scaleerrordrift Externalreference ±2 ±2 ppm/°C
Bipolarzeroerror(4) –4 4 –2 2 mV
Bipolarzeroerrordrift ±2 ±2 ppm/°C
Unipolarzero
error(4) 8.192V –20 6 20 –20 6 20 mV
Unipolarzeroerrordrift ±0.4 ±0.4 ppm/°C
Recoverytoratedaccuracyafter
1mFcapacitortoCAP 1 1 ms
powerdown
Powersupplysensitivity
(VDIG=VANA=VD) +4.75V<VD<+5.25V –8 8 –8 8 LSB
ACACCURACY
SFDR Spurious-freedynamicrange fI=20kHz 95 100 97 100 dB(6)
THD Totalharmonicdistortion fI=20kHz –96 –94 –98 –96 dB
fI=20kHz 87 91 90 92 dB
SINAD Signal-to-(noise+distortion)
–60dBInput 30 32 dB
SNR Signal-to-noiseratio fI=20kHz 88 92 91 93 dB
Full-powerbandwidth(7) 500 500 kHz
SAMPLINGDYNAMICS
Aperturedelay 5 5 ns
Transientresponse FSstep 2 2 ms
Overvoltagerecovery(8) 150 150 ns
REFERENCE
Internalreferencevoltage Noload 4.076 4.096 4.116 4.076 4.096 4.116 V
Internalreferencesourcecurrent
1 1 mA
(mustuseexternalbuffer)
Internalreferencedrift 8 8 ppm/°C
Externalreferencevoltagerange
3.9 4.096 4.2 3.9 4.096 4.2 V
forspecifiedlinearity
Externalreferencecurrentdrain External4.096Vref. 100 100 mA
(2) LSBmeansLeastSignificantBit.Forthe±10Vinputrange,oneLSBis305mV.
(3) Typicalrmsnoiseatworst-casetransitionsandtemperatures.
(4) AsmeasuredwithcircuitshowninFigure29andFigure30.
(5) Forbipolarinputranges,full-scaleerroristheworstcaseof–Full-Scaleor+Full-Scaleuncalibrateddeviationfromidealfirstandlast
codetransitions,dividedbythetransitionvoltage(notdividedbythefull-scalerange)andincludestheeffectofoffseterror.Forunipolar
inputranges,full-scaleerroristhedeviationofthelastcodetransitiondividedbythetransitionvoltage.Italsoincludestheeffectof
offseterror.
(6) AllspecificationsindBarereferredtoafull-scale±10Vinput.
(7) Full-powerbandwidthisdefinedasthefull-scaleinputfrequencyatwhichsignal-to-(noise+distortion)degradesto60dB.
(8) Recoverstospecifiedperformanceafter2xFSinputovervoltage.
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ELECTRICAL CHARACTERISTICS (continued)
AtT =–40°Cto+85°C,f =250kSPS,andV =V =5V,usinginternalreference(unlessotherwisespecified).
A s DIG ANA
ADS8519I ADS8519IB
PARAMETER TESTCONDITIONS MIN TYP MAX MIN TYP MAX UNIT
DIGITALINPUTS
Logiclevels
VIL Low-levelinputvoltage(9) VDIG=1.65Vto5.25V –0.3 0.6 –0.3 0.6 V
VIH High-levelinputvoltage(9) VDIG=1.65Vto5.25V 0.5xVDIG VDIG+0.3 0.5xVDIG VDIG+0.3 V
IIL Low-levelinputcurrent VIL=0V ±10 ±10 mA
IIH High-levelinputcurrent VIH=5V ±10 ±10 mA
DIGITALOUTPUTS
Dataformat Serial,16-bits Serial,16-bits
Binary2'scomplement Binary2'scomplement
Datacoding
orstraightbinary orstraightbinary
Conversionresultsonlyavailable Conversionresultsonlyavailable
Pipelinedelay
aftercompletedconversion aftercompletedconversion
Selectableforinternal Selectableforinternal
Dataclock
orexternaldataclock orexternaldataclock
Internalclock(outputonlywhen
EXT/INTlow 9 9 MHz
transmittingdata)
Externalclock(canrun
continuallybutnotrecommended EXT/INThigh 0.1 26 0.1 26 MHz
foroptimumperformance)
VOL Low-leveloutputvoltage IVSDINIGK==11..665mVA,to5.25V 0.45 0.45 V
VOH High-leveloutputvoltage IVSDOIUGR=CE1=.655V00tmoA5,.25V VDIG–0.45 VDIG–0.45 V
Hi-Zstate,
Leakagecurrent ±5 ±5 mA
VOUT=0VtoVDIG
Outputcapacitance Hi-Zstate 15 15 pF
POWERSUPPLIES
VDIG Digitalinputvoltage Mustbe≤VANA 1.65 5.25 1.65 5.25 V
VANA Analoginputvoltage Mustbe≤VANA 4.75 5 5.25 4.75 5 5.25 V
IDIG Digitalinputcurrent Mustbe≤VANA 0.1 1 0.1 1 mA
IANA Analoginputcurrent Mustbe≤VANA 22 25 22 25 mA
POWERDISSIPATION
PWRDLow fS=250kSPS 110 125 110 125 mW
PWRDHigh 20 20 mW
TEMPERATURERANGE
Specifiedperformance –40 +85 –40 +85 °C
Deratedperformance(10) –55 +125 –55 +125 °C
Storage –65 +150 –65 +150 °C
qJA Thermalresistance 67 67 °C/W
(9) TTL-compatibleat5Vsupply.
(10) Theinternalreferencemaynotbestartedcorrectlybeyondtheindustrialtemperaturerange(–40°Cto+85°C);therefore,useofan
externalreferenceisrecommended.
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PIN CONFIGURATION
DBPACKAGE
(TOPVIEW)
R1IN 1 28 VDIG
AGND1 2 27 VANA
R2IN 3 26 PWRD
R3IN 4 25 BUSY
NC 5 24 CS
CAP 6 23 NC
REF 7 22 NC
NC 8 21 R/C
AGND2 9 20 NC
NC 10 19 TAG
NC 11 18 NC
SB/BTC 12 17 DATA
EXT/INT 13 16 DATACLK
DGND 14 15 SYNC
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PinAssignments
PIN
NAME NO. I/O DESCRIPTION
AGND1 2 – Analogground.Usedinternallyasgroundreferencepoint.Minimalcurrentflow.
AGND2 9 – Analogground
Busyoutput.Fallswhenaconversionisstarted,andremainslowuntiltheconversioniscompletedand
BUSY 25 O
thedataarelatchedintotheoutputshiftregister.
CS 24 – Chipselect.InternallyORedwithR/C.
CAP 6 Referencebuffercapacitor,2.2mFtantalumcapacitortoground.
Serialdataoutput.DataaresynchronizedtoDATACLK,withtheformatdeterminedbythelevelof
SB/BTC.Intheexternalclockmode,after16bitsofdata,theADS8519outputsthelevelinputonTAG
DATA 17 O aslongasCSislowandR/Cishigh(seeFigure8andFigure9).IfEXT/INTislow,dataarevalidon
boththerisingandfallingedgesofDATACLK,andbetweenconversionsDATAstaysatthelevelofthe
TAGinputwhentheconversionwasstarted.
Eitheraninputoranoutput,dependingontheEXT/INTlevel.Outputdataaresynchronizedtothis
DATACLK 16 I/O clock.IfEXT/INTislow,DATACLKtransmits16pulsesaftereachconversion,andthenremainslow
betweenconversions.
DGND 14 – Digitalground
Selectsexternalorinternalclockfortransmittingdata.Ifhigh,dataareoutputsynchronizedtothe
EXT/INT 13 – clockinputonDATACLK.Iflow,aconvertcommandinitiatesthetransmissionofthedatafromthe
previousconversion,alongwith16clockpulsesoutputonDATACLK.
5,8,10,11,
NC 18,20,22, – Notconnected
23
Powerdowninput.Ifhigh,conversionsareinhibitedandpowerconsumptionissignificantlyreduced.
PWRD 26 I
Resultsfromthepreviousconversionaremaintainedintheoutputshiftregister.
Read/convertinput.WithCSlow,afallingedgeonR/Cputstheinternalsample-and-holdintothehold
stateandstartsaconversion.WhenEXT/INTislow,thisalsoinitiatesthetransmissionofthedata
R/C 21 I
resultsfromthepreviousconversion.IfEXT/INTishigh,arisingedgeonR/CwithCSlow,orafalling
edgeonCSwithR/Chigh,initiatesthetransmissionofdatafromthepreviousconversion.
Referenceinput/output.Outputsinternal4.096Vreference.Canalsobedrivenbyexternalsystem
REF 7 I/O
reference.Inbothcases,bypasstogroundwitha2.2mFtantalumcapacitor.
R1 1 I Analoginput.SeeTable2forinputrangeconnections.
IN
R2 3 I Analoginput.SeeTable2forinputrangeconnections.
IN
R3 4 I Analoginput.SeeTable2forinputrangeconnections.
IN
Selectstraightbinaryorbinarytwo'scomplementdataoutputformat.Ifhigh,dataareoutputina
SB/BTC 12 I
straightbinaryformat.Iflow,dataareoutputinabinarytwo'scomplementformat.
Syncoutput.ThispinisusedtosupplyadatasynchronizationpulsewhentheEXTlevelishighandat
SYNC 15 O leastoneexternalclockpulsehasoccurredwhennotinthereadmode.SeetheExternalDATACLK
sectionfortheexternalclockmodedescription.
Taginputforuseintheexternalclockmode.IfEXTishigh,digitaldatainputfromTAGisoutputon
TAG 19 I
DATAwithadelaythatdependsontheexternalclockmode.SeeFigure8andFigure9.
Analogsupplyinput.Nominally+5V.Connectdirectlytopin20,anddecoupletogroundwith0.1mF
V 27 I
ANA ceramicand10mFtantalumcapacitors.
V 28 I Digitalsupplyinput.Connectdirectlytopin19.
DIG
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TIMING REQUIREMENTS, T = –40°C to +85°C
A
PARAMETER MIN TYP MAX UNIT
t Pulseduration,convert 40 ns
w1
t Delaytime,BUSYfromR/Clow 6 20 ns
d1
t Pulseduration,BUSYlow 2.2 ms
w2
t Delaytime,BUSY,afterendofconversion 5 ns
d2
t Delaytime,aperture 5 ns
d3
t Conversiontime 2.2 ms
conv
t Acquisitiontime 1.8 ms
acq
t +t Cycletime 4 ms
conv acq
t Delaytime,R/CLowtointernalDATACLKoutput 270 ns
d4
t Cycletime,internalDATACLK 110 ns
c1
t Delaytime,datavalidtointernalDATACLKhigh 15 35 ns
d5
t Delaytime,datavalidafterinternalDATACLKlow 20 35 ns
d6
t Cycletime,externalDATACLK 35 ns
c2
t Pulseduration,externalDATACLKhigh 15 ns
w3
t Pulseduration,externalDATACLKlow 15 ns
w4
t Setuptime,R/Crise/falltoexternalDATACLKhigh 15 ns
su1
t Setuptime,R/CtransitiontoCStransition 10 ns
su2
t Delaytime,SYNC,afterexternalDATACLKhigh 3 35 ns
d7
t Delaytime,datavalidfromexternalDATACLKhigh 2 13 ns
d8
t Delaytime,CSrisingedgetoexternalDATACLKrisingedge 10 ns
d9
t Delaytime,previousdataavailableafterCS,R/Clow 2 ms
d10
t Setuptime,BUSYtransitiontofirstexternalDATACLK 5 ns
su3
t Delaytime,finalexternalDATACLKtoBUSYrisingedge 1 ms
d11
t Setuptime,TAGvalid 0 ns
su4
t Holdtime,TAGvalid 2 ns
h1
TIMING DIAGRAMS
CS R/C
R/C CS
tsu1 tsu1 tsu1 tsu1
External External
DATACLK DATACLK
CS Set Low, Discontinuous Ext DATACLK R/C Set Low, Discontinuous Ext DATACLK
CS BUSY
tsu2 tsu2 tsu3 1 2
External
R/C DATACLK
Setup Time, R/C to CS CS Set Low, Discontinuous Ext DATACLK
Figure1. CriticalTiming
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TIMING DIAGRAMS (continued)
tw1 tw1
R/C
td1 tw2 td1 tw2
BUSY
td3 tdt2d11 td3 td2td11
STATUS Nth Conversion ECrorrorrection (N+1)th Accquisition (N+1)th Conversion ECrorrorrection (N+2)th Accquisition
tconv tacq tconv tacq
td4 tc1 td4
Internal
DATACLK 1 2 16 1 2 16
td6
td5
DATA TAG = 0 D15 D0 TAG = 0 D15 D0 TAG = 0
(N−1)th Conversion Data Nth Conversion Data
CS, EXT/INT, and TAG are tied low
8starts READ
Figure2. BasicConversionTiming:InternalDATACLK(ReadPreviousDataDuringConversion)
tw1 tw1
R/C
td1 tw2 td1 tw2
BUSY
td2 td2
td3 td11 td3 td11
STATUS Nth Conversion Error (N+1)th Accquisition (N+1)th ConversionError (N+2)th Accquisition
Correction Correction
tconv tacq tconv tacq
tsu1 tsu3 tsu1 tsu3
External
DATACLK 1 16 1 2 16 1 16 1 2 16
No more No more
DATA TAG = 0 dshaitfat otout TAG = 0 Nth Data TAG = 0 dshaitfat otout TAG = 0 (N+1)th Data TAG = 0
EXT/INT tied high, CS and TAG are tied low tw1 + tsu1 starts READ
Figure3. BasicConversionTiming:ExternalDATACLK
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TIMING DIAGRAMS (continued)
tw1
R/C
td1 tw2 tsu1 td1
BUSY
td2
td3 td11 td3
STATUS Nth Conversion Error (N+1)th Accquisition
Correction
tconv tsu3 tacq
External tw3tc2 tw4 tsu1
DATACLK 0 1 2 3 4 5 10 11 12 13 14 15 16
SYNC = 0
td8 Nth Conversion Data td8
DATA D15 D14 D13 D12 D11 D10 D05 D04 D03 D02 D01 D00 Null T00 Txx
tsu4 th1
TAG T00 T01 T02 T03 T04 T05 T06 T11 T12 T13 T14 T15 T16 Null T17 Tyy
EXT/INT tied high, CS tied low
tw1 + tsu1 starts READ
Figure4. ReadAfter Conversion(DiscontinuousExternalDATACLK)
tw1
R/C
td1
tw2
BUSY
td3 td10 td2
Error
STATUS Nth Conversion
Correction
tsu3
tconv
tc2
tsu1 tw3 tw4 td11
External
DATACLK 0 1 2 3 4 5 10 11 12 13 14 15 16
SYNC = 0
td8 Nth Conversion Data td8
DATA D15 D14 D13 D12 D11 D10 D05 D04 D03 D02 D01 D00
EXT/INT tied high, CS and TAG tied low Rising DATACLK change DATA, tw1 + tsu1 Starts READ
TAG is not recommended for this mode. There is not enough
time to do so without violating td11.
Figure5. ReadDuringConversion(DiscontinuousExternalDATACLK)
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TIMING DIAGRAMS (continued)
tw1
R/C
td1 tsu1 tsu1 td1
tw2
BUSY
td2
td3 td11 td3
Error
STATUS Nth ConversionCorrection (N+1)th Accquisition
tconv tacq
tsu1 tsu3 tw3 tc2 tw4 tsu1
External
DATACLK 0 1 2 3 4 5 6 7 12 13 14 15 16 17 18
tc2
td7
SYNC=0
td8 Nth Conversion Data td8
DATA D15 D14 D13 D12 D11 D10 D05 D04 D03 D02 D01 D00 Null T00 Txx
tsu4 th1
TAG T00 T01 T02 T03 T04 T05 T06 T11 T12 T13 T14 T15 T16 T17 Tyy
EXT/INT tied high, CS tied low tw1 + tsu1 starts READ
Figure6. ReadAfterConversionWithSYNC(DiscontinuousExternalDATACLK)
tw1
R/C
td1
tw2
BUSY
td3 td10 td2
Error
STATUS Nth Conversion Correction
tsu3
tconv
Externtsaul1 tsu1 tsu1 tw3 ttcw24 td11
DATACLK 0 1 2 3 4 5 6 7 12 13 14 15 16 17 18
td7
tc2
SYNC = 0
td8 Nth Conversion Data td8
DATA D15 D14 D13 D12 D11 D10 D05 D04 D03 D02 D01 D00
tw1 + tsu1 Starts READ
EXT/INT tied high, CS and TAG tied low TAG is not recommended for this mode. There is not enough
time to do so without violating td11.
Figure7. ReadDuringConversionWithSYNC(DiscontinuousExternalDATACLK)
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